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* aarch64/fpu: Add vector variants of powJoe Ramsay2024-05-211-1/+5
| | | | | | | Plus a small amount of moving includes around in order to be able to remove duplicate definition of asuint64. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of cbrtJoe Ramsay2024-05-161-0/+1
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of hypotJoe Ramsay2024-05-161-0/+1
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of erfcJoe Ramsay2024-04-041-1/+4
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of tanhJoe Ramsay2024-04-041-1/+2
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of sinhJoe Ramsay2024-04-041-0/+1
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of atanhJoe Ramsay2024-04-041-0/+1
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of asinhJoe Ramsay2024-04-041-0/+1
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of acoshJoe Ramsay2024-04-041-0/+1
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of coshJoe Ramsay2024-04-041-1/+3
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64/fpu: Add vector variants of erfJoe Ramsay2024-04-041-1/+6
| | | | Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64: Add vector implementations of expm1 routinesJoe Ramsay2023-11-201-0/+1
| | | | May discard sign of 0 - auto tests for -0 and -0x1p-10000 updated accordingly.
* aarch64: Add vector implementations of log1p routinesJoe Ramsay2023-11-101-0/+1
| | | | May discard sign of zero.
* aarch64: Add vector implementations of atan2 routinesJoe Ramsay2023-11-101-0/+1
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* aarch64: Add vector implementations of atan routinesJoe Ramsay2023-11-101-0/+1
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* aarch64: Add vector implementations of acos routinesJoe Ramsay2023-11-101-1/+2
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* aarch64: Add vector implementations of asin routinesJoe Ramsay2023-11-101-1/+2
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* aarch64: Add vector implementations of exp10 routinesJoe Ramsay2023-10-231-0/+1
| | | | | Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.
* aarch64: Add vector implementations of log10 routinesJoe Ramsay2023-10-231-1/+3
| | | | A table is also added, which is shared between AdvSIMD and SVE log10.
* aarch64: Add vector implementations of log2 routinesJoe Ramsay2023-10-231-1/+3
| | | | A table is also added, which is shared between AdvSIMD and SVE log2.
* aarch64: Add vector implementations of exp2 routinesJoe Ramsay2023-10-231-0/+1
| | | | Some routines reuse table from v_exp_data.c
* aarch64: Add vector implementations of tan routinesJoe Ramsay2023-10-231-1/+2
| | | | | This includes some utility headers for evaluating polynomials using various schemes.
* aarch64: Add vector implementations of exp routinesJoe Ramsay2023-06-301-1/+3
| | | | | | | | | | | | Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64: Add vector implementations of log routinesJoe Ramsay2023-06-301-1/+3
| | | | | | | | | | | | | | Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. Log lookup table added as HIDDEN symbol to allow it to be shared between AdvSIMD and SVE variants. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64: Add vector implementations of sin routinesJoe Ramsay2023-06-301-6/+6
| | | | | | | | | | | | Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* Enable libmvec support for AArch64Joe Ramsay2023-05-031-0/+61
| | | | | | | | | | | | | | | | | | | | | | | This patch enables libmvec on AArch64. The proposed change is mainly implementing build infrastructure to add the new routines to ABI, tests and benchmarks. I have demonstrated how this all fits together by adding implementations for vector cos, in both single and double precision, targeting both Advanced SIMD and SVE. The implementations of the routines themselves are just loops over the scalar routine from libm for now, as we are more concerned with getting the plumbing right at this point. We plan to contribute vector routines from the Arm Optimized Routines repo that are compliant with requirements described in the libmvec wiki. Building libmvec requires minimum GCC 10 for SVE ACLE. To avoid raising the minimum GCC by such a big jump, we allow users to disable libmvec if their compiler is too old. Note that at this point users have to manually call the vector math functions. This seems to be acceptable to some downstream users. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64: Remove fpu MakefileAdhemerval Zanella2020-06-221-14/+0
| | | | | | | | The -fno-math-errno is already added by default and the minimum required GCC to build glibc (6.2) make the -ffinite-math-only superflous. Checked on aarch64-linux-gnu.
* aarch64: Fix f{max,min}{f} build for GCC 4.9 and 5Adhemerval Zanella2017-11-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | GCC 4.9 and 5 do not generate a correct f{max,min}nm instruction for __builtin_{fmax,fmin}{f} without -ffinite-math-only. It is clear a compiler issue since the instruction can handle NaN and Inf correctly and GCC6+ does not show this issue. We can backport a fix to GCC 5, raise the minimum required GCC version for aarch64 (since GCC 4.9 branch is now closed [1]) and/or add configure check to check for this issue. However I think -ffinite-math-only should be safe for these specific implementations and it is a simpler solution. Checked on aarch64-linux-gnu with GCC 5.3.1. * sysdeps/aarch64/fpu/Makefile (CFLAGS-s_fmax.c, CFLAGS-s_fmaxf.c, CFLAGS-s_fmin.c, CFLAGS-s_fminf.c): New rule: add -ffinite-math-only. [1] https://gcc.gnu.org/ml/gcc/2016-08/msg00010.html Signed-off-by: Adhemerval Zanella <adhemerval.zanella@linaro.org> Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
* aarch64: Add missing math Makefile for recent commitSzabolcs Nagy2017-10-231-0/+8
Without -fno-math-errno, the builtins just do a call instead of inlining a single instruction.
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