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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 09:45:41 -0600 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 12:58:33 -0600 |
| commit | 4393fc119c34e97519b9b7a4fc94066b283be452 (patch) | |
| tree | dffac0629930499b0f88886fca4f1b094ef74fa5 /sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c | |
| parent | 487972aea52004f604c2878c8c9d3e77670f2c32 (diff) | |
| download | glibc-4393fc119c34e97519b9b7a4fc94066b283be452.tar.gz glibc-4393fc119c34e97519b9b7a4fc94066b283be452.tar.xz glibc-4393fc119c34e97519b9b7a4fc94066b283be452.zip | |
PowerPC: Optimized isinf/isinff for POWER8
This patch add a optimized isinf/isinff implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c b/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c index 1336feb015..71da7a3c77 100644 --- a/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c +++ b/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c @@ -24,10 +24,13 @@ extern __typeof (__isinff) __isinff_ppc64 attribute_hidden; /* The double-precision version also works for single-precision. */ extern __typeof (__isinff) __isinf_power7 attribute_hidden; +extern __typeof (__isinff) __isinf_power8 attribute_hidden; libc_ifunc (__isinff, - (hwcap & PPC_FEATURE_ARCH_2_06) - ? __isinf_power7 + (hwcap2 & PPC_FEATURE2_ARCH_2_07) + ? __isinf_power8 : + (hwcap & PPC_FEATURE_ARCH_2_06) + ? __isinf_power7 : __isinff_ppc64); weak_alias (__isinff, isinff) |