From 4393fc119c34e97519b9b7a4fc94066b283be452 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella Date: Thu, 27 Feb 2014 09:45:41 -0600 Subject: PowerPC: Optimized isinf/isinff for POWER8 This patch add a optimized isinf/isinff implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move. --- sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c') diff --git a/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c b/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c index 1336feb015..71da7a3c77 100644 --- a/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c +++ b/sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c @@ -24,10 +24,13 @@ extern __typeof (__isinff) __isinff_ppc64 attribute_hidden; /* The double-precision version also works for single-precision. */ extern __typeof (__isinff) __isinf_power7 attribute_hidden; +extern __typeof (__isinff) __isinf_power8 attribute_hidden; libc_ifunc (__isinff, - (hwcap & PPC_FEATURE_ARCH_2_06) - ? __isinf_power7 + (hwcap2 & PPC_FEATURE2_ARCH_2_07) + ? __isinf_power8 : + (hwcap & PPC_FEATURE_ARCH_2_06) + ? __isinf_power7 : __isinff_ppc64); weak_alias (__isinff, isinff) -- cgit 1.4.1