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| author | Xi Ruoyao <xry111@xry111.site> | 2024-06-13 19:04:05 +0800 |
|---|---|---|
| committer | caiyinyu <caiyinyu@loongson.cn> | 2024-06-14 10:14:54 +0800 |
| commit | 97aa7b7346bb9f1807e450c889fccbd2a7d8ff49 (patch) | |
| tree | 1ff3164154544026329c681a2743a0a7aaa85799 /sysdeps/loongarch/sys/asm.h | |
| parent | 868ab8923a2ec977faafec97ecafac0c3159c1b2 (diff) | |
| download | glibc-97aa7b7346bb9f1807e450c889fccbd2a7d8ff49.tar.gz glibc-97aa7b7346bb9f1807e450c889fccbd2a7d8ff49.tar.xz glibc-97aa7b7346bb9f1807e450c889fccbd2a7d8ff49.zip | |
LoongArch: Ensure sp 16-byte aligned for tlsdesc
"ADDI sp, sp, 24" and "ADDI sp, sp, SZFCSREG" (SZFCSREG = 4) are misaligning the stack: the ABI mandates a 16-byte alignment. Fix it by changing the first one to "ADDI sp, sp, 32", and reuse the spare 4th slot for saving fcsr. Reported-by: Jinyang He <hejinyang@loongson.cn> Signed-off-by: Xi Ruoyao <xry111@xry111.site>
Diffstat (limited to 'sysdeps/loongarch/sys/asm.h')
| -rw-r--r-- | sysdeps/loongarch/sys/asm.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/sysdeps/loongarch/sys/asm.h b/sysdeps/loongarch/sys/asm.h index 23c1d12914..51521a7eb4 100644 --- a/sysdeps/loongarch/sys/asm.h +++ b/sysdeps/loongarch/sys/asm.h @@ -25,7 +25,6 @@ /* Macros to handle different pointer/register sizes for 32/64-bit code. */ #define SZREG 8 #define SZFREG 8 -#define SZFCSREG 4 #define SZVREG 16 #define SZXREG 32 #define REG_L ld.d |