From 97aa7b7346bb9f1807e450c889fccbd2a7d8ff49 Mon Sep 17 00:00:00 2001 From: Xi Ruoyao Date: Thu, 13 Jun 2024 19:04:05 +0800 Subject: LoongArch: Ensure sp 16-byte aligned for tlsdesc "ADDI sp, sp, 24" and "ADDI sp, sp, SZFCSREG" (SZFCSREG = 4) are misaligning the stack: the ABI mandates a 16-byte alignment. Fix it by changing the first one to "ADDI sp, sp, 32", and reuse the spare 4th slot for saving fcsr. Reported-by: Jinyang He Signed-off-by: Xi Ruoyao --- sysdeps/loongarch/sys/asm.h | 1 - 1 file changed, 1 deletion(-) (limited to 'sysdeps/loongarch/sys/asm.h') diff --git a/sysdeps/loongarch/sys/asm.h b/sysdeps/loongarch/sys/asm.h index 23c1d12914..51521a7eb4 100644 --- a/sysdeps/loongarch/sys/asm.h +++ b/sysdeps/loongarch/sys/asm.h @@ -25,7 +25,6 @@ /* Macros to handle different pointer/register sizes for 32/64-bit code. */ #define SZREG 8 #define SZFREG 8 -#define SZFCSREG 4 #define SZVREG 16 #define SZXREG 32 #define REG_L ld.d -- cgit 1.4.1