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| author | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2017-10-23 20:22:42 +0530 |
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| committer | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2017-10-23 20:23:35 +0530 |
| commit | a2e0a7f12ba57a49d1380c7ba1ff4b1f51d67347 (patch) | |
| tree | e2082ffded8ed105c418278713345e4043b8b77e /ChangeLog | |
| parent | db9bab09a51188bf57afeb47040ce6837b878367 (diff) | |
| download | glibc-a2e0a7f12ba57a49d1380c7ba1ff4b1f51d67347.tar.gz glibc-a2e0a7f12ba57a49d1380c7ba1ff4b1f51d67347.tar.xz glibc-a2e0a7f12ba57a49d1380c7ba1ff4b1f51d67347.zip | |
aarch64: Document _SC_LEVEL1_DCACHE_LINESIZE caveat
The _SC_LEVEL1_DCACHE_LINESIZE is reported using the contents of the ctr_el0 register, which tells us the minimum observable cache line size by userspace. This typically is the same as the L1 cache line size, but that may not always be true. It could be a higher level cache line size as long as cache cleaning and invalidation work correctly with that line size in userspace. The falkor core for example reports the L2 line size as the dcache line size in CTR_EL0 while also reporting the correct L1 dcache line size via CCSIDR_EL1. * manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat. Reviewed-by: Rical Jasan <ricaljasan@pacific.net> Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 890443736b..b756f97aa4 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,8 @@ 2017-10-23 Siddhesh Poyarekar <siddhesh@sourceware.org> + * manual/conf.texi (_SC_LEVEL1_DCACHE_LINESIZE, + _SC_LEVEL1_ICACHE_LINESIZE): Document aarch64 caveat. + * manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE, _SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE, _SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC, |