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| author | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2017-10-23 20:19:34 +0530 |
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| committer | Siddhesh Poyarekar <siddhesh@sourceware.org> | 2017-10-23 20:23:13 +0530 |
| commit | db9bab09a51188bf57afeb47040ce6837b878367 (patch) | |
| tree | c8cf726159cb485d1fa9b755a300404ad90bb7d8 /ChangeLog | |
| parent | be080b6c143901d998c91f28ef7b2fe4a25c0237 (diff) | |
| download | glibc-db9bab09a51188bf57afeb47040ce6837b878367.tar.gz glibc-db9bab09a51188bf57afeb47040ce6837b878367.tar.xz glibc-db9bab09a51188bf57afeb47040ce6837b878367.zip | |
Document cache information sysconf variables
Write short descriptions for each of the cache information sysconf variables. * manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE, _SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE, _SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC, _SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE, _SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE, _SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC, _SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE, _SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New variables. Reviewed-by: Rical Jasan <ricaljasan@pacific.net>
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 1316b401ae..890443736b 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,15 @@ +2017-10-23 Siddhesh Poyarekar <siddhesh@sourceware.org> + + * manual/conf.texi (_SC_LEVEL1_ICACHE_SIZE, + _SC_LEVEL1_ICACHE_ASSOC, _SC_LEVEL1_ICACHE_LINESIZE, + _SC_LEVEL1_DCACHE_SIZE, _SC_LEVEL1_DCACHE_ASSOC, + _SC_LEVEL1_DCACHE_LINESIZE, _SC_LEVEL2_CACHE_SIZE, + _SC_LEVEL2_CACHE_ASSOC, _SC_LEVEL2_CACHE_LINESIZE, + _SC_LEVEL3_CACHE_SIZE, _SC_LEVEL3_CACHE_ASSOC, + _SC_LEVEL3_CACHE_LINESIZE, _SC_LEVEL4_CACHE_SIZE, + _SC_LEVEL4_CACHE_ASSOC, _SC_LEVEL4_CACHE_LINESIZE): New + variables. + 2017-10-23 Michael Collison <michael.collison@arm.com> * sysdeps/aarch64/fpu/e_sqrt.c (ieee754_sqrt): Replace asm statements |