diff options
| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 09:45:41 -0600 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 12:58:33 -0600 |
| commit | 4393fc119c34e97519b9b7a4fc94066b283be452 (patch) | |
| tree | dffac0629930499b0f88886fca4f1b094ef74fa5 /ChangeLog | |
| parent | 487972aea52004f604c2878c8c9d3e77670f2c32 (diff) | |
| download | glibc-4393fc119c34e97519b9b7a4fc94066b283be452.tar.gz glibc-4393fc119c34e97519b9b7a4fc94066b283be452.tar.xz glibc-4393fc119c34e97519b9b7a4fc94066b283be452.zip | |
PowerPC: Optimized isinf/isinff for POWER8
This patch add a optimized isinf/isinff implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index 45e17cc31a..39bc73d5e5 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,19 @@ 2014-02-27 Adhemerval Zanella <azanella@linux.vnet.ibm.com> + * sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile: Add isinf power8 + implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf-power8.S: New file: + POWER8 isinf ifunc implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf.c (__isinf): Add + POWER8 implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c (__isinff): + Likewise. + * sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S: New file: + POWER8 isinf implementation. + * sysdeps/powerpc/powerpc64/power8/fpu/s_isinff.S: New file. + +2014-02-27 Adhemerval Zanella <azanella@linux.vnet.ibm.com> + * sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h (INIT_ARCH): Add hwcap2 initialization. * sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile: Add isnan power8 |