From 4393fc119c34e97519b9b7a4fc94066b283be452 Mon Sep 17 00:00:00 2001 From: Adhemerval Zanella Date: Thu, 27 Feb 2014 09:45:41 -0600 Subject: PowerPC: Optimized isinf/isinff for POWER8 This patch add a optimized isinf/isinff implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move. --- ChangeLog | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'ChangeLog') diff --git a/ChangeLog b/ChangeLog index 45e17cc31a..39bc73d5e5 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,17 @@ +2014-02-27 Adhemerval Zanella + + * sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile: Add isinf power8 + implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf-power8.S: New file: + POWER8 isinf ifunc implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinf.c (__isinf): Add + POWER8 implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_isinff.c (__isinff): + Likewise. + * sysdeps/powerpc/powerpc64/power8/fpu/s_isinf.S: New file: + POWER8 isinf implementation. + * sysdeps/powerpc/powerpc64/power8/fpu/s_isinff.S: New file. + 2014-02-27 Adhemerval Zanella * sysdeps/powerpc/powerpc32/power4/multiarch/init-arch.h (INIT_ARCH): -- cgit 1.4.1