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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-18 09:29:29 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 12:58:33 -0600 |
| commit | 1ad8950a3ea4056ed343d681b5146f4b4aa27e10 (patch) | |
| tree | 4dff22d7793de4244498f8c384dea196eb47a5a1 /ChangeLog | |
| parent | cac626d60a863e48ab75417064984769e58c5719 (diff) | |
| download | glibc-1ad8950a3ea4056ed343d681b5146f4b4aa27e10.tar.gz glibc-1ad8950a3ea4056ed343d681b5146f4b4aa27e10.tar.xz glibc-1ad8950a3ea4056ed343d681b5146f4b4aa27e10.zip | |
PowerPC: llrint/llrintf POWER8 optimization
This patch add a optimized llrint/llrintf implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move.
Diffstat (limited to 'ChangeLog')
| -rw-r--r-- | ChangeLog | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/ChangeLog b/ChangeLog index ee2ed4ed0b..8912bb7512 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,16 @@ 2014-02-27 Adhemerval Zanella <azanella@linux.vnet.ibm.com> + * sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile: Add llrint power8 + implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint-power8.S: New file: + POWER8 llrint ifunc implementation. + * sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c (__lllrint): Add + POWER8 implementation. + * sysdeps/powerpc/powerpc64/power8/fpu/s_llrint.S: New file: + POWER8 llrint implementation. + +2014-02-27 Adhemerval Zanella <azanella@linux.vnet.ibm.com> + * sysdeps/powerpc/powerpc64/fpu/multiarch/Makefile: Add finite power8 implementation. * sysdeps/powerpc/powerpc64/fpu/multiarch/s_finite-power8.S: New file: |