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* add SPE FPU support to powerpc-sfRich Felker2021-09-232-2/+2
| | | | | | | | | | | | | | | | | | | When the soft-float ABI for PowerPC was added in commit 5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb, with Freescale cpus using the alternative SPE FPU as the main use case, it was noted that we could probably support hard float on them, but that it would involve determining some difficult ABI constraints. This commit is the completion of that work. The Power-Arch-32 ABI supplement defines the ABI profiles, and indeed ATR-SPE is built on ATR-SOFT-FLOAT. But setjmp/longjmp compatibility are problematic for the same reason they're problematic on ARM, where optional float-related parts of the register file are "call-saved if present". This requires testing __hwcap, which is now done. In keeping with the existing powerpc-sf subarch definition, which did not have fenv, the fenv macros are not defined for SPE and the SPEFSCR control register is left (and assumed to start in) the default mode.
* fix sh fesetround failure to clear old modeRich Felker2020-04-181-0/+2
| | | | | | the sh version of fesetround or'd the new rounding mode onto the control register without clearing the old rounding mode bits, making changes sticky. this was the root cause of multiple test failures.
* riscv64: fix fesetenv(FE_DFL_ENV) crashRuinland ChuanTzu Tsai2019-12-071-1/+4
| | | | | When FE_DFL_ENV is passed to fesetenv(), the very first instruction lw t1, 0(a0) will fail since a0 is -1.
* add riscv64 architecture supportRich Felker2019-06-142-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Author: Alex Suykov <alex.suykov@gmail.com> Author: Aric Belsito <lluixhi@gmail.com> Author: Drew DeVault <sir@cmpwn.com> Author: Michael Clark <mjc@sifive.com> Author: Michael Forney <mforney@mforney.org> Author: Stefan O'Rear <sorear2@gmail.com> This port has involved the work of many people over several years. I have tried to ensure that everyone with substantial contributions has been credited above; if any omissions are found they will be noted later in an update to the authors/contributors list in the COPYRIGHT file. The version committed here comes from the riscv/riscv-musl repo's commit 3fe7e2c75df78eef42dcdc352a55757729f451e2, with minor changes by me for issues found during final review: - a_ll/a_sc atomics are removed (according to the ISA spec, lr/sc are not safe to use in separate inline asm fragments) - a_cas[_p] is fixed to be a memory barrier - the call from the _start assembly into the C part of crt1/ldso is changed to allow for the possibility that the linker does not place them nearby each other. - DTP_OFFSET is defined correctly so that local-dynamic TLS works - reloc.h LDSO_ARCH logic is simplified and made explicit. - unused, non-functional crti/n asm files are removed. - an empty .sdata section is added to crt1 so that the __global_pointer reference is resolvable. - indentation style errors in some asm files are fixed.
* fix fesetround error checkingSzabolcs Nagy2018-10-101-6/+5
| | | | Rounding modes are not bit flags, but arbitrary non-negative integers.
* reduce spurious inclusion of libc.hRich Felker2018-09-124-4/+4
| | | | | | | | | | | | | | | | | | | | | libc.h was intended to be a header for access to global libc state and related interfaces, but ended up included all over the place because it was the way to get the weak_alias macro. most of the inclusions removed here are places where weak_alias was needed. a few were recently introduced for hidden. some go all the way back to when libc.h defined CANCELPT_BEGIN and _END, and all (wrongly implemented) cancellation points had to include it. remaining spurious users are mostly callers of the LOCK/UNLOCK macros and files that use the LFS64 macro to define the awful *64 aliases. in a few places, new inclusion of libc.h is added because several internal headers no longer implicitly include libc.h. declarations for __lockfile and __unlockfile are moved from libc.h to stdio_impl.h so that the latter does not need libc.h. putting them in libc.h made no sense at all, since the macros in stdio_impl.h are needed to use them correctly anyway.
* make arch __fesetround backends hiddenRich Felker2018-09-1214-4/+18
| | | | | these are not public interfaces and do not match the public function, but delegate argument checking to it.
* add m68k portRich Felker2018-06-191-0/+84
| | | | | | | | | | | | | three ABIs are supported: the default with 68881 80-bit fpu format and results returned in floating point registers, softfloat-only with the same format, and coldfire fpu with IEEE single/double only. only the first is tested at all, and only under qemu which has fpu emulation bugs. basic functionality smoke tests have been performed for the most common arch-specific breakage via libc-test and qemu user-level emulation. some sysvipc failures remain, but are shared with other big endian archs and will be fixed separately.
* add s390x portBobby Bingham2016-11-111-0/+55
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* add powerpc64 portBobby Bingham2016-05-081-0/+68
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* add mips n32 port (ILP32 ABI for mips64)Rich Felker2016-04-182-0/+73
| | | | based on patch submitted by Jaydeep Patil, with minor changes.
* add powerpc soft-float supportFelix Fietkau2016-03-062-18/+27
| | | | | | | | | Some PowerPC CPUs (e.g. Freescale MPC85xx) have a completely different instruction set for floating point operations (SPE). Executing regular PowerPC floating point instructions results in "Illegal instruction" errors. Make it possible to run these devices in soft-float mode.
* add mips64 portRich Felker2016-03-062-0/+74
| | | | | patch by Mahesh Bodapati and Jaydeep Patil of Imagination Technologies.
* switch arm, sh, and mips fenv asm from .sub system to .S filesRich Felker2016-01-2012-6/+21
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* explicitly assemble all arm asm sources as UALRich Felker2015-11-101-0/+1
| | | | | | | | these files are all accepted as legacy arm syntax when producing arm code, but legacy syntax cannot be used for producing thumb2 with access to the full ISA. even after switching to UAL, some asm source files contain instructions which are not valid in thumb mode, so these will need to be addressed separately.
* use vfp mnemonics instead of p10 coprocessor ones in armhf fenv asmSzabolcs Nagy2015-11-051-10/+10
| | | | | mrc/mcr p10 coprocessor mnemonics are deprecated by some toolchains.
* declare fpu usage to the assembler in arm hard-float asm filesSzabolcs Nagy2015-10-191-0/+2
| | | | | | | Some armhf gcc toolchains (built with --with-float=hard but without --with-fpu=vfp*) do not pass -mfpu=vfp to the assembler and then binutils rejects the UAL mnemonics for VFP unless there is an .fpu vfp directive in the asm source.
* fix mips fesetround failure to write back resulting modeRich Felker2015-10-011-0/+1
| | | | patch by Anand Takale.
* fix mips fesetenv(FE_DFL_ENV) againRich Felker2015-04-171-0/+1
| | | | | commit 5fc1487832e16aa2119e735a388d5f36c8c139e2 attempted to fix it, but neglected the fact that mips has branch delay slots.
* add aarch64 portSzabolcs Nagy2015-03-111-0/+67
| | | | | | | | | | This adds complete aarch64 target support including bigendian subarch. Some of the long double math functions are known to be broken otherwise interfaces should be fully functional, but at this point consider this port experimental. Initial work on this port was done by Sireesh Tripurari and Kevin Bortis.
* fix FLT_ROUNDS to reflect the current rounding modeSzabolcs Nagy2015-03-071-0/+19
| | | | | Implemented as a wrapper around fegetround introducing a new function to the ABI: __flt_rounds. (fegetround cannot be used directly from float.h)
* simplify armhf fesetenvSzabolcs Nagy2015-02-081-1/+0
| | | | armhf fesetenv implementation did a useless read of the fpscr.
* fix fesetenv(FE_DFL_ENV) on mipsSzabolcs Nagy2015-02-081-1/+3
| | | | | mips fesetenv did not handle FE_DFL_ENV, now fcsr is cleared in that case.
* add nofpu subarchs to the sh arch, and properly detect compiler's fpu configRich Felker2014-02-272-0/+2
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* rename superh port to "sh" for consistencyRich Felker2014-02-271-0/+0
| | | | | | | | | linux, gcc, etc. all use "sh" as the name for the superh arch. there was already some inconsistency internally in musl: the dynamic linker was searching for "ld-musl-sh.path" as its path file despite its own name being "ld-musl-superh.so.1". there was some sentiment in both directions as to how to resolve the inconsistency, but overall "sh" was favored.
* add missing sub files for mipsel-sf to use softfloat codeRich Felker2014-02-241-0/+1
| | | | | | the build system has no automatic way to know this code applies to both big (default) and little endian variants, so explicit .sub files are needed.
* mips: add mips-sf subarch support (soft-float)Szabolcs Nagy2014-02-241-0/+1
| | | | | | | | | Userspace emulated floating-point (gcc -msoft-float) is not compatible with the default mips abi (assumes an FPU or in kernel emulation of it). Soft vs hard float abi should not be mixed, __mips_soft_float is checked in musl's configure script and there is no runtime check. The -sf subarch does not save/restore floating-point registers in setjmp/longjmp and only provides dummy fenv implementation.
* superh portBobby Bingham2014-02-231-0/+74
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* x32 port (diff against vanilla x86_64)rofl0r2014-02-231-26/+26
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* import vanilla x86_64 code as x32rofl0r2014-02-231-0/+97
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* fix fesetenv(FE_DFL_ENV) on x86_64 (see previous commit)Szabolcs Nagy2014-02-091-1/+1
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* fix fesetenv(FE_DFL_ENV) on i386Szabolcs Nagy2014-02-091-1/+1
| | | | | | | | | | | the default fenv was not set up properly, in particular the tag word that indicates the contents of the x87 registers was set to 0 (used) instead of 0xffff (empty) this could cause random crashes after setting the default fenv because it corrupted the fpu stack and then any float computation gives NaN result breaking the program logic (usually after a float to integer conversion).
* fenv: fix i386 fesetround for sseSzabolcs Nagy2013-10-281-1/+1
| | | | | | i386 fenv code checks __hwcap for sse support, but in fesetround the sse code was unconditionally jumped over after the test so the sse rounding mode was never set.
* fix invalid instruction mnemonics in powerpc fenv asmRich Felker2013-08-271-3/+3
| | | | | there is no non-dot version of the andis instruction, but there's no harm in updating the flags anyway, so just use the dot version.
* fix fenv exception functions to mask their argumentSzabolcs Nagy2013-08-188-18/+55
| | | | | | | | | | | fesetround.c is a wrapper to do the arch independent argument check (on archs where rounding mode is not stored in 2 bits __fesetround still has to check its arguments) on powerpc fe*except functions do not accept the extra invalid flags of its fpscr register the useless FENV_ACCESS pragma was removed from feupdateenv
* optimize x86 feclearexcept: only use save/restore x87 fenv if neededSzabolcs Nagy2013-08-182-27/+38
| | | | | | | the x87 exception summary (ES) and stack fault (SF) flags may be spuriously cleared by feclearexcept using the fnclex instruction, but these flags are not observable through libc hence maintaining their state is not critical.
* add sse fenv support on i386 through hwcapSzabolcs Nagy2013-08-182-9/+61
| | | | | | | the sse and x87 rounding modes should be always the same, the visible exception flags are the bitwise or of the two fenv states (so it's enough to query the rounding mode or raise exceptions on one fenv)
* fix i386 fesetenv: FE_DFL_ENV is (fenv_t*)-1 not 0Szabolcs Nagy2013-08-181-2/+2
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* support floating point environment (fenv) on armhf (hard float) subarchsRich Felker2013-08-163-0/+62
| | | | | patch by nsz. I've tested it on an armhf machine and it seems to be working correctly.
* fenv support for ppc, untestedRich Felker2012-11-181-0/+120
| | | | based on code sent to the mailing list by nsz, with minor changes.
* fix feholdexcept -- it needs to clear exceptions after saving environmentRich Felker2012-11-181-0/+1
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* fenv: return FE_TONEAREST in dummy fegetroundSzabolcs Nagy2012-11-141-1/+1
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* math: use '#pragma STDC FENV_ACCESS ON' when fenv is accessedSzabolcs Nagy2012-11-131-0/+1
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* floating point environment/exceptions support for mipsRich Felker2012-10-181-0/+60
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* try fixing/optimizing x86_64 fenv exception codeRich Felker2012-03-171-18/+23
| | | | untested; may need followup-fixes.
* optimize x86 feclearexceptRich Felker2012-03-171-16/+20
| | | | | if all exception flags will be cleared, we can avoid the expensive store/reload of the environment and just use the fnclex instruction.
* fix x86_64 fe[gs]etround, analogous to nsz's x86 changesRich Felker2012-03-171-8/+9
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* minor 387 fenv optimizationsRich Felker2012-03-171-6/+5
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* fix i386 fegetround and make fesetround fasternsz2012-03-171-10/+10
| | | | | | | | | | | | | | | | | | | | | Note that the new fesetround has slightly different semantics: Storing the floating-point environment with fnstenv makes the next fldenv (or fldcw) "non-signaling", so unmasked and pending exceptions does not invoke the exception handler. (These are rare since exceptions are handled immediately and by default all exceptions are masked anyway. But if one manually unmasks an exception in the control word then either sets the corresponding exception flag in the status word or the execution of an exception raising floating-point operation gets interrupted then it may happen). So the old implementation did not trap in some rare cases where the new implementation traps. However POSIX does not specify anything like the x87 exception handling traps and the fnstenv/fldenv pair is significantly slower than the fnstcw/fldcw pair (new code is about 5x faster here and it's dominated by the function call overhead).
* use type directives for fenv asm functionsRich Felker2011-06-282-0/+14
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