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| author | Rich Felker <dalias@aerifal.cx> | 2019-05-24 10:46:08 -0400 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2019-06-14 17:13:05 -0400 |
| commit | 0a48860c27a8eb291bcc7616ea9eb073dc660cab (patch) | |
| tree | 6021d6d18943d7b883e38e2f3e20a3b81d916fc5 /src/fenv | |
| parent | 5fc43798250255455e4b5f9b08000bd3102274d9 (diff) | |
| download | musl-0a48860c27a8eb291bcc7616ea9eb073dc660cab.tar.gz musl-0a48860c27a8eb291bcc7616ea9eb073dc660cab.tar.xz musl-0a48860c27a8eb291bcc7616ea9eb073dc660cab.zip | |
add riscv64 architecture support
Author: Alex Suykov <alex.suykov@gmail.com> Author: Aric Belsito <lluixhi@gmail.com> Author: Drew DeVault <sir@cmpwn.com> Author: Michael Clark <mjc@sifive.com> Author: Michael Forney <mforney@mforney.org> Author: Stefan O'Rear <sorear2@gmail.com> This port has involved the work of many people over several years. I have tried to ensure that everyone with substantial contributions has been credited above; if any omissions are found they will be noted later in an update to the authors/contributors list in the COPYRIGHT file. The version committed here comes from the riscv/riscv-musl repo's commit 3fe7e2c75df78eef42dcdc352a55757729f451e2, with minor changes by me for issues found during final review: - a_ll/a_sc atomics are removed (according to the ISA spec, lr/sc are not safe to use in separate inline asm fragments) - a_cas[_p] is fixed to be a memory barrier - the call from the _start assembly into the C part of crt1/ldso is changed to allow for the possibility that the linker does not place them nearby each other. - DTP_OFFSET is defined correctly so that local-dynamic TLS works - reloc.h LDSO_ARCH logic is simplified and made explicit. - unused, non-functional crti/n asm files are removed. - an empty .sdata section is added to crt1 so that the __global_pointer reference is resolvable. - indentation style errors in some asm files are fixed.
Diffstat (limited to 'src/fenv')
| -rw-r--r-- | src/fenv/riscv64/fenv-sf.c | 3 | ||||
| -rw-r--r-- | src/fenv/riscv64/fenv.S | 53 |
2 files changed, 56 insertions, 0 deletions
diff --git a/src/fenv/riscv64/fenv-sf.c b/src/fenv/riscv64/fenv-sf.c new file mode 100644 index 00000000..ecd3cb5c --- /dev/null +++ b/src/fenv/riscv64/fenv-sf.c @@ -0,0 +1,3 @@ +#ifndef __riscv_flen +#include "../fenv.c" +#endif diff --git a/src/fenv/riscv64/fenv.S b/src/fenv/riscv64/fenv.S new file mode 100644 index 00000000..f149003d --- /dev/null +++ b/src/fenv/riscv64/fenv.S @@ -0,0 +1,53 @@ +#ifdef __riscv_flen + +.global feclearexcept +.type feclearexcept, %function +feclearexcept: + csrc fflags, a0 + li a0, 0 + ret + +.global feraiseexcept +.type feraiseexcept, %function +feraiseexcept: + csrs fflags, a0 + li a0, 0 + ret + +.global fetestexcept +.type fetestexcept, %function +fetestexcept: + frflags t0 + and a0, t0, a0 + ret + +.global fegetround +.type fegetround, %function +fegetround: + frrm a0 + ret + +.global __fesetround +.type __fesetround, %function +__fesetround: + fsrm t0, a0 + li a0, 0 + ret + +.global fegetenv +.type fegetenv, %function +fegetenv: + frcsr t0 + sw t0, 0(a0) + li a0, 0 + ret + +.global fesetenv +.type fesetenv, %function +fesetenv: + lw t1, 0(a0) + fscsr t0, t1 + li a0, 0 + ret + +#endif |