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authorRich Felker <dalias@aerifal.cx>2019-05-22 15:17:12 -0400
committerRich Felker <dalias@aerifal.cx>2019-05-22 15:17:12 -0400
commit3c59a868956636bc8adafb1b168d090897692532 (patch)
treed6aa3ab65678f8cad5d6655ddf7723b283fc6751 /src/signal/sigdelset.c
parenta60b9e06861e56c0810bae0249b421e1758d281a (diff)
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fix vrregset_t layout and member naming on powerpc64
the mistaken layout seems to have been adapted from 32-bit powerpc,
where vscr and vrsave are packed into the same 128-bit slot in a way
that looks like it relies on non-overlapping-ness of the value bits in
big endian.

the powerpc64 port accounted for the fact that the 64-bit ABI puts
each in its own 128-bit slot, but ordered them incorrectly (matching
the bit order used on the 32-bit ABI), and failed to account for vscr
being padded according to endianness so that it can be accessed via
vector moves.

in addition to ABI layout, our definition used different logical
member layout/naming from glibc, where vscr is a structure to
facilitate access as a 32-bit word or a 128-bit vector. the
inconsistency here was unintentional, so fix it.
Diffstat (limited to 'src/signal/sigdelset.c')
0 files changed, 0 insertions, 0 deletions