add riscv64 architecture support

Author: Alex Suykov <alex.suykov@gmail.com>
Author: Aric Belsito <lluixhi@gmail.com>
Author: Drew DeVault <sir@cmpwn.com>
Author: Michael Clark <mjc@sifive.com>
Author: Michael Forney <mforney@mforney.org>
Author: Stefan O'Rear <sorear2@gmail.com>

This port has involved the work of many people over several years. I
have tried to ensure that everyone with substantial contributions has
been credited above; if any omissions are found they will be noted
later in an update to the authors/contributors list in the COPYRIGHT
file.

The version committed here comes from the riscv/riscv-musl repo's
commit 3fe7e2c75df78eef42dcdc352a55757729f451e2, with minor changes by
me for issues found during final review:

- a_ll/a_sc atomics are removed (according to the ISA spec, lr/sc
  are not safe to use in separate inline asm fragments)

- a_cas[_p] is fixed to be a memory barrier

- the call from the _start assembly into the C part of crt1/ldso is
  changed to allow for the possibility that the linker does not place
  them nearby each other.

- DTP_OFFSET is defined correctly so that local-dynamic TLS works

- reloc.h LDSO_ARCH logic is simplified and made explicit.

- unused, non-functional crti/n asm files are removed.

- an empty .sdata section is added to crt1 so that the
  __global_pointer reference is resolvable.

- indentation style errors in some asm files are fixed.

2 files changed, 83 insertions, 0 deletions

diff --git a/src/setjmp/riscv64/longjmp.S b/src/setjmp/riscv64/longjmp.S
new file mode 100644
index 00000000..41e2d210
--- /dev/null
+++ b/src/setjmp/riscv64/longjmp.S
@@ -0,0 +1,42 @@
+.global __longjmp
+.global _longjmp
+.global longjmp
+.type __longjmp, %function
+.type _longjmp,  %function
+.type longjmp,   %function
+__longjmp:
+_longjmp:
+longjmp:
+	ld s0,    0(a0)
+	ld s1,    8(a0)
+	ld s2,    16(a0)
+	ld s3,    24(a0)
+	ld s4,    32(a0)
+	ld s5,    40(a0)
+	ld s6,    48(a0)
+	ld s7,    56(a0)
+	ld s8,    64(a0)
+	ld s9,    72(a0)
+	ld s10,   80(a0)
+	ld s11,   88(a0)
+	ld sp,    96(a0)
+	ld ra,    104(a0)
+
+#ifndef __riscv_float_abi_soft
+	fld fs0,  112(a0)
+	fld fs1,  120(a0)
+	fld fs2,  128(a0)
+	fld fs3,  136(a0)
+	fld fs4,  144(a0)
+	fld fs5,  152(a0)
+	fld fs6,  160(a0)
+	fld fs7,  168(a0)
+	fld fs8,  176(a0)
+	fld fs9,  184(a0)
+	fld fs10, 192(a0)
+	fld fs11, 200(a0)
+#endif
+
+	seqz a0, a1
+	add a0, a0, a1
+	ret
diff --git a/src/setjmp/riscv64/setjmp.S b/src/setjmp/riscv64/setjmp.S
new file mode 100644
index 00000000..51249672
--- /dev/null
+++ b/src/setjmp/riscv64/setjmp.S
@@ -0,0 +1,41 @@
+.global __setjmp
+.global _setjmp
+.global setjmp
+.type __setjmp, %function
+.type _setjmp,  %function
+.type setjmp,   %function
+__setjmp:
+_setjmp:
+setjmp:
+	sd s0,    0(a0)
+	sd s1,    8(a0)
+	sd s2,    16(a0)
+	sd s3,    24(a0)
+	sd s4,    32(a0)
+	sd s5,    40(a0)
+	sd s6,    48(a0)
+	sd s7,    56(a0)
+	sd s8,    64(a0)
+	sd s9,    72(a0)
+	sd s10,   80(a0)
+	sd s11,   88(a0)
+	sd sp,    96(a0)
+	sd ra,    104(a0)
+
+#ifndef __riscv_float_abi_soft
+	fsd fs0,  112(a0)
+	fsd fs1,  120(a0)
+	fsd fs2,  128(a0)
+	fsd fs3,  136(a0)
+	fsd fs4,  144(a0)
+	fsd fs5,  152(a0)
+	fsd fs6,  160(a0)
+	fsd fs7,  168(a0)
+	fsd fs8,  176(a0)
+	fsd fs9,  184(a0)
+	fsd fs10, 192(a0)
+	fsd fs11, 200(a0)
+#endif
+
+	li a0, 0
+	ret