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| author | Rich Felker <dalias@aerifal.cx> | 2021-09-23 19:11:46 -0400 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2021-09-23 19:11:46 -0400 |
| commit | 7be59733d71ada3a32a98622507399253f1d5e48 (patch) | |
| tree | 8baa69b0f4bb7dacacee7f8a8650e8f951614d0b /src/setjmp/powerpc/longjmp.S | |
| parent | e3e7189c11d909199155327fd6a93dcc6b68c7b3 (diff) | |
| download | musl-7be59733d71ada3a32a98622507399253f1d5e48.tar.gz musl-7be59733d71ada3a32a98622507399253f1d5e48.tar.xz musl-7be59733d71ada3a32a98622507399253f1d5e48.zip | |
add SPE FPU support to powerpc-sf
When the soft-float ABI for PowerPC was added in commit 5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb, with Freescale cpus using the alternative SPE FPU as the main use case, it was noted that we could probably support hard float on them, but that it would involve determining some difficult ABI constraints. This commit is the completion of that work. The Power-Arch-32 ABI supplement defines the ABI profiles, and indeed ATR-SPE is built on ATR-SOFT-FLOAT. But setjmp/longjmp compatibility are problematic for the same reason they're problematic on ARM, where optional float-related parts of the register file are "call-saved if present". This requires testing __hwcap, which is now done. In keeping with the existing powerpc-sf subarch definition, which did not have fenv, the fenv macros are not defined for SPE and the SPEFSCR control register is left (and assumed to start in) the default mode.
Diffstat (limited to 'src/setjmp/powerpc/longjmp.S')
| -rw-r--r-- | src/setjmp/powerpc/longjmp.S | 32 |
1 files changed, 31 insertions, 1 deletions
diff --git a/src/setjmp/powerpc/longjmp.S b/src/setjmp/powerpc/longjmp.S index e598bd05..34aecb4c 100644 --- a/src/setjmp/powerpc/longjmp.S +++ b/src/setjmp/powerpc/longjmp.S @@ -37,7 +37,37 @@ longjmp: lwz 29, 72(3) lwz 30, 76(3) lwz 31, 80(3) -#ifndef _SOFT_FLOAT +#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__) + mflr 0 + bl 1f + .hidden __hwcap + .long __hwcap-. +1: mflr 4 + lwz 5, 0(4) + add 4, 4, 5 + andis. 4, 4, 0x80 + beq 1f + .long 0x11c35b01 /* evldd 14,88(3) */ + .long 0x11e36301 /* ... */ + .long 0x12036b01 + .long 0x12237301 + .long 0x12437b01 + .long 0x12638301 + .long 0x12838b01 + .long 0x12a39301 + .long 0x12c39b01 + .long 0x12e3a301 + .long 0x1303ab01 + .long 0x1323b301 + .long 0x1343bb01 + .long 0x1363c301 + .long 0x1383cb01 + .long 0x13a3d301 + .long 0x13c3db01 + .long 0x13e3e301 /* evldd 31,224(3) */ + .long 0x11a3eb01 /* evldd 13,232(3) */ +1: mtlr 0 +#else lfd 14,88(3) lfd 15,96(3) lfd 16,104(3) |