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| author | Stefan O'Rear <sorear@fastmail.com> | 2020-09-03 05:45:44 -0400 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2024-02-29 16:36:55 -0500 |
| commit | b4f7b2ca350ccaa6f58ecec72ac46b7aef22d1c3 (patch) | |
| tree | 4568548c4c055336520eaeb49534bc570a177ee5 /src/fenv | |
| parent | 01d9fe4d9f7cce7a6dbaece0e2e405a2e3279244 (diff) | |
| download | musl-b4f7b2ca350ccaa6f58ecec72ac46b7aef22d1c3.tar.gz musl-b4f7b2ca350ccaa6f58ecec72ac46b7aef22d1c3.tar.xz musl-b4f7b2ca350ccaa6f58ecec72ac46b7aef22d1c3.zip | |
riscv32: add fenv and math
These are identical to riscv64.
Diffstat (limited to 'src/fenv')
| -rw-r--r-- | src/fenv/riscv32/fenv-sf.c | 3 | ||||
| -rw-r--r-- | src/fenv/riscv32/fenv.S | 56 |
2 files changed, 59 insertions, 0 deletions
diff --git a/src/fenv/riscv32/fenv-sf.c b/src/fenv/riscv32/fenv-sf.c new file mode 100644 index 00000000..ecd3cb5c --- /dev/null +++ b/src/fenv/riscv32/fenv-sf.c @@ -0,0 +1,3 @@ +#ifndef __riscv_flen +#include "../fenv.c" +#endif diff --git a/src/fenv/riscv32/fenv.S b/src/fenv/riscv32/fenv.S new file mode 100644 index 00000000..0ea78bf9 --- /dev/null +++ b/src/fenv/riscv32/fenv.S @@ -0,0 +1,56 @@ +#ifdef __riscv_flen + +.global feclearexcept +.type feclearexcept, %function +feclearexcept: + csrc fflags, a0 + li a0, 0 + ret + +.global feraiseexcept +.type feraiseexcept, %function +feraiseexcept: + csrs fflags, a0 + li a0, 0 + ret + +.global fetestexcept +.type fetestexcept, %function +fetestexcept: + frflags t0 + and a0, t0, a0 + ret + +.global fegetround +.type fegetround, %function +fegetround: + frrm a0 + ret + +.global __fesetround +.type __fesetround, %function +__fesetround: + fsrm t0, a0 + li a0, 0 + ret + +.global fegetenv +.type fegetenv, %function +fegetenv: + frcsr t0 + sw t0, 0(a0) + li a0, 0 + ret + +.global fesetenv +.type fesetenv, %function +fesetenv: + li t2, -1 + li t1, 0 + beq a0, t2, 1f + lw t1, 0(a0) +1: fscsr t1 + li a0, 0 + ret + +#endif |