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authorHongliang Wang <wanghongliang@loongson.cn>2023-09-26 09:12:01 +0800
committerRich Felker <dalias@aerifal.cx>2024-02-16 09:33:10 -0500
commit522bd54edaa2fa404fd428f8ad0bcb0f0bec5639 (patch)
treedfe88361bcbbd17ac53b8af36cb52337f21095e9 /src/fenv
parent4a16ddf53e7c634169d0a649782f8a724611f263 (diff)
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add loongarch64 port
Author: Xiaojuan Zhai <zhaixiaojuan@loongson.cn>
Author: Meidan Li <limeidan@loongson.cn>
Author: Guoqi Chen <chenguoqi@loongson.cn>
Author: Xiaolin Zhao <zhaoxiaolin@loongson.cn>
Author: Fan peng <fanpeng@loongson.cn>
Author: Jiantao Shan <shanjiantao@loongson.cn>
Author: Xuhui Qiang <qiangxuhui@loongson.cn>
Author: Jingyun Hua <huajingyun@loongson.cn>
Author: Liu xue <liuxue@loongson.cn>
Author: Hongliang Wang <wanghongliang@loongson.cn>
Diffstat (limited to 'src/fenv')
-rw-r--r--src/fenv/loongarch64/fenv.S78
1 files changed, 78 insertions, 0 deletions
diff --git a/src/fenv/loongarch64/fenv.S b/src/fenv/loongarch64/fenv.S
new file mode 100644
index 00000000..9c38599e
--- /dev/null
+++ b/src/fenv/loongarch64/fenv.S
@@ -0,0 +1,78 @@
+#ifndef __loongarch_soft_float
+
+#ifdef BROKEN_LOONGARCH_FCSR_ASM
+#define FCSR $r0
+#else
+#define FCSR $fcsr0
+#endif
+
+.global feclearexcept
+.type   feclearexcept,@function
+feclearexcept:
+	li.w    $t0, 0x1f0000
+	and     $a0, $a0, $t0
+	movfcsr2gr $t1, FCSR
+	andn    $t1, $t1, $a0
+	movgr2fcsr FCSR, $t1
+	li.w    $a0, 0
+	jr      $ra
+
+.global feraiseexcept
+.type   feraiseexcept,@function
+feraiseexcept:
+	li.w    $t0, 0x1f0000
+	and     $a0, $a0, $t0
+	movfcsr2gr $t1, FCSR
+	or      $t1, $t1, $a0
+	movgr2fcsr FCSR, $t1
+	li.w    $a0, 0
+	jr      $ra
+
+.global fetestexcept
+.type   fetestexcept,@function
+fetestexcept:
+	li.w    $t0, 0x1f0000
+	and     $a0, $a0, $t0
+	movfcsr2gr $t1, FCSR
+	and     $a0, $t1, $a0
+	jr      $ra
+
+.global fegetround
+.type   fegetround,@function
+fegetround:
+	movfcsr2gr $t0, FCSR
+	andi    $a0, $t0, 0x300
+	jr      $ra
+
+.global __fesetround
+.hidden __fesetround
+.type   __fesetround,@function
+__fesetround:
+	li.w    $t0, 0x300
+	and     $a0, $a0, $t0
+	movfcsr2gr $t1, FCSR
+	andn    $t1, $t1, $t0
+	or      $t1, $t1, $a0
+	movgr2fcsr FCSR, $t1
+	li.w    $a0, 0
+	jr      $ra
+
+.global fegetenv
+.type   fegetenv,@function
+fegetenv:
+	movfcsr2gr $t0, FCSR
+	st.w    $t0, $a0, 0
+	li.w    $a0, 0
+	jr      $ra
+
+.global fesetenv
+.type   fesetenv,@function
+fesetenv:
+	addi.d  $t0, $a0, 1
+	beq     $t0, $r0, 1f
+	ld.w    $t0, $a0, 0
+1:	movgr2fcsr FCSR, $t0
+	li.w    $a0, 0
+	jr      $ra
+
+#endif