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authorRich Felker <dalias@aerifal.cx>2012-09-29 01:05:31 -0400
committerRich Felker <dalias@aerifal.cx>2012-09-29 01:05:31 -0400
commit8c0a3d9e5c169fc9d0f246ab59362b658b029ad7 (patch)
tree6ac54202768db511e8bb959d85060adb98cbf226 /crt/microblaze
parente0ea44cb764fcdbe8515f22096930bede2c7896f (diff)
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microblaze port
based on initial work by rdp, with heavy modifications. some features
including threads are untested because qemu app-level emulation seems
to be broken and I do not have a proper system image for testing.
Diffstat (limited to 'crt/microblaze')
-rw-r--r--crt/microblaze/crt1.s16
-rw-r--r--crt/microblaze/crti.s13
-rw-r--r--crt/microblaze/crtn.s9
3 files changed, 38 insertions, 0 deletions
diff --git a/crt/microblaze/crt1.s b/crt/microblaze/crt1.s
new file mode 100644
index 00000000..33090bba
--- /dev/null
+++ b/crt/microblaze/crt1.s
@@ -0,0 +1,16 @@
+.weak  _init
+.weak  _fini
+.global _start
+.align  2
+_start:
+	add     r19, r0, r0             # Zero the frame pointer.
+	ori     r5, r0, main            # Get main() ...
+	lw      r6, r0, r1              # Get argc...
+	addi    r7, r1, 4               # ... and argv ...
+	ori     r8, r0, _init           # and _init() ...
+	ori     r9, r0, _fini           # and _fini() ...
+	add     r10, r0, r0             # ldso_fini == NULL
+	andi    r1, r1, -8              # align stack
+	addik   r1, r1, -4*6            # Leave space for the args.
+	bri     __libc_start_main       # Let's go!
+	nop                             # Never gets here.
diff --git a/crt/microblaze/crti.s b/crt/microblaze/crti.s
new file mode 100644
index 00000000..ed1c2fa4
--- /dev/null
+++ b/crt/microblaze/crti.s
@@ -0,0 +1,13 @@
+.section .init
+.global _init
+.align 2
+_init:
+	addi r1, r1, -32
+	swi r15, r1, 0
+
+.section .fini
+.global _fini
+.align 2
+_fini:
+	addi r1, r1, -32
+	swi r15, r1, 0
diff --git a/crt/microblaze/crtn.s b/crt/microblaze/crtn.s
new file mode 100644
index 00000000..1e02c984
--- /dev/null
+++ b/crt/microblaze/crtn.s
@@ -0,0 +1,9 @@
+.section .init
+	lwi r15, r1, 0
+	rtsd r15, 8
+	addi r1, r1, 32
+
+.section .fini
+	lwi r15, r1, 0
+	rtsd r15, 8
+	addi r1, r1, 32