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authorLuís Marques <luismarques@lowrisc.org>2020-01-15 13:24:41 +0000
committerRich Felker <dalias@aerifal.cx>2020-01-22 14:57:16 -0500
commit83350eb17b9cb355e3f08b0340c4f1e8c437fac9 (patch)
tree5e75c517d1c19035dc03373503f58b2febff0c2c /arch
parenta2e71304f358c5dbaf44e0b4c6fd343e8cd236e2 (diff)
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fix riscv64 a_cas inline asm operand sign extension
This patch adds an explicit cast to the int arguments passed to the
inline asm used in the RISC-V's implementation of `a_cas`, to ensure
that they are properly sign extended to 64 bits. They aren't
automatically sign extended by Clang, and GCC technically also doesn't
guarantee that they will be sign extended.
Diffstat (limited to 'arch')
-rw-r--r--arch/riscv64/atomic_arch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
index 41ad4d04..0c382588 100644
--- a/arch/riscv64/atomic_arch.h
+++ b/arch/riscv64/atomic_arch.h
@@ -15,7 +15,7 @@ static inline int a_cas(volatile int *p, int t, int s)
 		"	bnez %1, 1b\n"
 		"1:"
 		: "=&r"(old), "=&r"(tmp)
-		: "r"(p), "r"(t), "r"(s)
+		: "r"(p), "r"((long)t), "r"((long)s)
 		: "memory");
 	return old;
 }