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author | Rich Felker <dalias@aerifal.cx> | 2024-02-29 11:02:29 -0500 |
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committer | Rich Felker <dalias@aerifal.cx> | 2024-02-29 16:36:55 -0500 |
commit | 3ea3fcf78a5532e118856846df8adbf3f60ef716 (patch) | |
tree | afb3892aac50017bea2f71fbd8067a39886a8447 /arch | |
parent | b28c44de8c3131b45588f61569b1711c987ba1c3 (diff) | |
download | musl-3ea3fcf78a5532e118856846df8adbf3f60ef716.tar.gz musl-3ea3fcf78a5532e118856846df8adbf3f60ef716.tar.xz musl-3ea3fcf78a5532e118856846df8adbf3f60ef716.zip |
riscv32: add sysvipc msg/sem/shm bits
despite riscv32 being natively time64, the IPC_TIME64 bit (0x100) is set in IPC_STAT and derived command macros, differentiating their values from the raw command values used to interface with the kernel. this reflects that the kernel ipc structure types are not natively time64, but have broken-down hi/lo fields that cannot be used in-place and require translation, and that the userspace struct types differ from the kernel types (relevant to things like strace).
Diffstat (limited to 'arch')
-rw-r--r-- | arch/riscv32/bits/ipcstat.h | 1 | ||||
-rw-r--r-- | arch/riscv32/bits/msg.h | 18 | ||||
-rw-r--r-- | arch/riscv32/bits/sem.h | 18 | ||||
-rw-r--r-- | arch/riscv32/bits/shm.h | 31 |
4 files changed, 68 insertions, 0 deletions
diff --git a/arch/riscv32/bits/ipcstat.h b/arch/riscv32/bits/ipcstat.h new file mode 100644 index 00000000..4f4fcb0c --- /dev/null +++ b/arch/riscv32/bits/ipcstat.h @@ -0,0 +1 @@ +#define IPC_STAT 0x102 diff --git a/arch/riscv32/bits/msg.h b/arch/riscv32/bits/msg.h new file mode 100644 index 00000000..7bbbb2bf --- /dev/null +++ b/arch/riscv32/bits/msg.h @@ -0,0 +1,18 @@ +struct msqid_ds { + struct ipc_perm msg_perm; + unsigned long __msg_stime_lo; + unsigned long __msg_stime_hi; + unsigned long __msg_rtime_lo; + unsigned long __msg_rtime_hi; + unsigned long __msg_ctime_lo; + unsigned long __msg_ctime_hi; + unsigned long msg_cbytes; + msgqnum_t msg_qnum; + msglen_t msg_qbytes; + pid_t msg_lspid; + pid_t msg_lrpid; + unsigned long __unused[2]; + time_t msg_stime; + time_t msg_rtime; + time_t msg_ctime; +}; diff --git a/arch/riscv32/bits/sem.h b/arch/riscv32/bits/sem.h new file mode 100644 index 00000000..544e3d2a --- /dev/null +++ b/arch/riscv32/bits/sem.h @@ -0,0 +1,18 @@ +struct semid_ds { + struct ipc_perm sem_perm; + unsigned long __sem_otime_lo; + unsigned long __sem_otime_hi; + unsigned long __sem_ctime_lo; + unsigned long __sem_ctime_hi; +#if __BYTE_ORDER == __LITTLE_ENDIAN + unsigned short sem_nsems; + char __sem_nsems_pad[sizeof(long)-sizeof(short)]; +#else + char __sem_nsems_pad[sizeof(long)-sizeof(short)]; + unsigned short sem_nsems; +#endif + long __unused3; + long __unused4; + time_t sem_otime; + time_t sem_ctime; +}; diff --git a/arch/riscv32/bits/shm.h b/arch/riscv32/bits/shm.h new file mode 100644 index 00000000..725fb469 --- /dev/null +++ b/arch/riscv32/bits/shm.h @@ -0,0 +1,31 @@ +#define SHMLBA 4096 + +struct shmid_ds { + struct ipc_perm shm_perm; + size_t shm_segsz; + unsigned long __shm_atime_lo; + unsigned long __shm_atime_hi; + unsigned long __shm_dtime_lo; + unsigned long __shm_dtime_hi; + unsigned long __shm_ctime_lo; + unsigned long __shm_ctime_hi; + pid_t shm_cpid; + pid_t shm_lpid; + unsigned long shm_nattch; + unsigned long __pad1; + unsigned long __pad2; + unsigned long __pad3; + time_t shm_atime; + time_t shm_dtime; + time_t shm_ctime; +}; + +struct shminfo { + unsigned long shmmax, shmmin, shmmni, shmseg, shmall, __unused[4]; +}; + +struct shm_info { + int __used_ids; + unsigned long shm_tot, shm_rss, shm_swp; + unsigned long __swap_attempts, __swap_successes; +}; |