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* <sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu2021-01-2112-832/+1153
* x86: Move x86 processor cache info to cpu_featuresH.J. Lu2021-01-145-412/+551
* Fix x86 build with --enable-tunable=noAdhemerval Zanella2021-01-141-0/+1
* ldconfig/x86: Store ISA level in cache and aux cacheH.J. Lu2021-01-131-0/+31
* x86: Set header.feature_1 in TCB for always-on CET [BZ #27177]H.J. Lu2021-01-133-1/+11
* x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]H.J. Lu2021-01-0717-41/+607
* Drop nan-pseudo-number.h usage from testsSiddhesh Poyarekar2021-01-041-1/+0
* Update copyright dates with scripts/update-copyrightsPaul Eggert2021-01-0281-81/+81
* x86 long double: Consider pseudo numbers as signalingSiddhesh Poyarekar2020-12-301-0/+30
* Remove _ISOMAC check from <cpu-features.h>H.J. Lu2020-12-241-81/+75
* x86: Remove the duplicated CPU_FEATURE_CPU_PH.J. Lu2020-12-241-2/+0
* Partially revert 681900d29683722b1cb0a8e565a0585846ec5a61Siddhesh Poyarekar2020-12-242-12/+1
* x86 long double: Support pseudo numbers in isnanlSiddhesh Poyarekar2020-12-241-0/+45
* x86 long double: Support pseudo numbers in fpclassifylSiddhesh Poyarekar2020-12-241-0/+46
* <sys/platform/x86.h>: Add Intel LAM supportH.J. Lu2020-12-222-0/+4
* x86: Remove the default REP MOVSB threshold tunable value [BZ #27061]H.J. Lu2020-12-141-2/+4
* elf: Pass the fd to note processingSzabolcs Nagy2020-12-111-3/+3
* x86: Adjust tst-cpu-features-supports.c for GCC 11H.J. Lu2020-12-041-5/+10
* x86: Set RDRAND usable if CPU supports RDRANDH.J. Lu2020-12-041-0/+1
* x86: Remove UP macro. Define LOCK_PREFIX unconditionally.Florian Weimer2020-11-131-7/+1
* x86: Restore processing of cache size tunables in init_cacheinfoFlorian Weimer2020-10-281-8/+4
* x86: Optimizing memcpy for AMD Zen architecture.Sajan Karumanchi2020-10-281-6/+26
* x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu2020-10-167-857/+943
* <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM supportH.J. Lu2020-10-093-0/+18
* <sys/platform/x86.h>: Add Intel HRESET supportH.J. Lu2020-10-092-0/+4
* <sys/platform/x86.h>: Add AVX-VNNI supportH.J. Lu2020-10-093-0/+7
* <sys/platform/x86.h>: Add AVX512_FP16 supportH.J. Lu2020-10-093-3/+7
* <sys/platform/x86.h>: Add Intel UINTR supportH.J. Lu2020-10-092-3/+4
* Reversing calculation of __x86_shared_non_temporal_thresholdPatrick McGehearty2020-09-281-5/+11
* x86: Harden printf against non-normal long double values (bug 26649)Florian Weimer2020-09-223-0/+64
* x86: Use one ldbl2mpn.c file for both i386 and x86_64Florian Weimer2020-09-221-0/+120
* x86: Use HAS_CPU_FEATURE with IBT and SHSTK [BZ #26625]H.J. Lu2020-09-173-6/+4
* <sys/platform/x86.h>: Add Intel Key Locker supportH.J. Lu2020-09-163-3/+42
* x86: Install <sys/platform/x86.h> [BZ #26124]H.J. Lu2020-09-118-141/+654
* x86: Set CPU usable feature bits conservatively [BZ #26552]H.J. Lu2020-09-031-96/+47
* x86: Rename Intel CPU feature namesH.J. Lu2020-08-052-15/+15
* x86: Support usable check for all CPU featuresH.J. Lu2020-07-136-439/+561
* x86: Remove __ASSEMBLER__ check in init-arch.hH.J. Lu2020-07-111-5/+1
* x86: Remove the unused __x86_prefetchwH.J. Lu2020-07-112-16/+4
* rtld: Clean up PT_NOTE and add PT_GNU_PROPERTY handlingSzabolcs Nagy2020-07-081-40/+7
* x86: Add thresholds for "rep movsb/stosb" to tunablesH.J. Lu2020-07-064-0/+68
* x86: Detect Extended Feature Disable (XFD)H.J. Lu2020-07-062-0/+4
* x86: Correct bit_cpu_CLFSH [BZ #26208]H.J. Lu2020-07-061-1/+1
* x86: Detect Intel Advanced Matrix ExtensionsH.J. Lu2020-06-263-0/+44
* x86: Update CPU feature detection [BZ #26149]H.J. Lu2020-06-224-389/+267
* i386: Use builtin sqrtlAdhemerval Zanella2020-06-221-0/+27
* x86: Update F16C detection [BZ #26133]H.J. Lu2020-06-182-3/+7
* x86: Correct bit_cpu_CLFLUSHOPT [BZ #26128]H.J. Lu2020-06-171-1/+1
* x86: Update Intel Atom processor family optimizationH.J. Lu2020-05-211-1/+19
* x86: Add --enable-cet=permissiveH.J. Lu2020-05-186-43/+69
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