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* x86/cet: Run some CET tests with shadow stackH.J. Lu2024-01-014-0/+17
* x86/cet: Don't set CET active by defaultH.J. Lu2024-01-012-2/+15
* x86/cet: Check feature_1 in TCB for active IBT and SHSTKH.J. Lu2024-01-013-1/+35
* x86/cet: Enable shadow stack during startupH.J. Lu2024-01-016-93/+93
* x86/cet: Sync with Linux kernel 6.6 shadow stack interfaceH.J. Lu2024-01-012-6/+11
* x86/cet: Don't disable CET if not single threadedH.J. Lu2023-12-201-2/+9
* x86: Modularize sysdeps/x86/dl-cet.cH.J. Lu2023-12-201-176/+280
* Fix elf: Do not duplicate the GLIBC_TUNABLES stringH.J. Lu2023-12-191-1/+1
* Fix elf: Do not duplicate the GLIBC_TUNABLES stringH.J. Lu2023-12-191-5/+5
* i686: Do not raise exception traps on fesetexcept (BZ 30989)Adhemerval Zanella2023-12-191-18/+5
* elf: Do not duplicate the GLIBC_TUNABLES stringAdhemerval Zanella2023-12-193-75/+193
* x86/cet: Check CPU_FEATURE_ACTIVE in permissive modeH.J. Lu2023-12-192-0/+6
* x86/cet: Check legacy shadow stack code in .init_array sectionH.J. Lu2023-12-1911-0/+330
* x86/cet: Add tests for GLIBC_TUNABLES=glibc.cpu.hwcaps=-SHSTKH.J. Lu2023-12-193-0/+28
* x86/cet: Check CPU_FEATURE_ACTIVE when CET is disabledH.J. Lu2023-12-193-0/+9
* x86/cet: Check legacy shadow stack applicationsH.J. Lu2023-12-196-0/+130
* x86/cet: Don't assume that SHSTK implies IBTH.J. Lu2023-12-183-11/+11
* x86/cet: Check user_shstk in /proc/cpuinfoH.J. Lu2023-12-171-1/+1
* x86: Check PT_GNU_PROPERTY earlyH.J. Lu2023-12-111-40/+80
* sysdeps/x86/Makefile: Split and sort testsH.J. Lu2023-12-111-32/+78
* x86: Use dl-symbol-redir-ifunc.h on cpu-tunablesAdhemerval Zanella2023-11-211-27/+12
* x86: Add support for AVX10 preset and vec size in cpu-featuresNoah Goldstein2023-09-294-3/+71
* x86: Check the lower byte of EAX of CPUID leaf 2 [BZ #30643]H.J. Lu2023-08-291-18/+13
* x86: Fix incorrect scope of setting `shared_per_thread` [BZ# 30745]Noah Goldstein2023-08-111-4/+3
* x86: Fix for cache computation on AMD legacy cpus.Sajan Karumanchi2023-08-061-27/+199
* <sys/platform/x86.h>: Add APX supportH.J. Lu2023-07-274-0/+11
* [PATCH v1] x86: Use `3/4*sizeof(per-thread-L3)` as low bound for NT threshold.Noah Goldstein2023-07-181-3/+12
* x86: Fix slight bug in `shared_per_thread` cache size calculation.Noah Goldstein2023-07-181-2/+2
* configure: Use autoconf 2.71Siddhesh Poyarekar2023-07-171-46/+52
* x86: Make dl-cache.h and readelflib.c not Linux-specificSergey Bugaev2023-06-261-0/+90
* Fix misspellings -- BZ 25337Paul Pluzhnikov2023-06-192-2/+2
* x86: Make the divisor in setting `non_temporal_threshold` cpu specificNoah Goldstein2023-06-124-26/+51
* x86: Refactor Intel `init_cpu_features`Noah Goldstein2023-06-121-81/+309
* x86: Increase `non_temporal_threshold` to roughly `sizeof_L3 / 4`Noah Goldstein2023-06-121-27/+43
* Fix a few more typos I missed in previous round -- BZ 25337Paul Pluzhnikov2023-06-021-1/+1
* Fix misspellings in sysdeps/ -- BZ 25337Paul Pluzhnikov2023-05-303-3/+3
* x86: Use 64MB as nt-store threshold if no cacheinfo [BZ #30429]Noah Goldstein2023-05-271-1/+9
* <sys/platform/x86.h>: Add PREFETCHI supportH.J. Lu2023-04-054-0/+7
* <sys/platform/x86.h>: Add AMX-COMPLEX supportH.J. Lu2023-04-054-0/+8
* <sys/platform/x86.h>: Add AVX-NE-CONVERT supportH.J. Lu2023-04-054-0/+8
* <sys/platform/x86.h>: Add AVX-VNNI-INT8 supportH.J. Lu2023-04-054-0/+17
* <sys/platform/x86.h>: Add MSRLIST supportH.J. Lu2023-04-052-0/+2
* <sys/platform/x86.h>: Add AVX-IFMA supportH.J. Lu2023-04-054-0/+8
* <sys/platform/x86.h>: Add AMX-FP16 supportH.J. Lu2023-04-054-0/+8
* <sys/platform/x86.h>: Add WRMSRNS supportH.J. Lu2023-04-052-0/+2
* <sys/platform/x86.h>: Add ArchPerfmonExt supportH.J. Lu2023-04-052-0/+2
* <sys/platform/x86.h>: Add CMPCCXADD supportH.J. Lu2023-04-054-0/+7
* <sys/platform/x86.h>: Add LASS supportH.J. Lu2023-04-052-0/+2
* <sys/platform/x86.h>: Add RAO-INT supportH.J. Lu2023-04-054-0/+7
* <sys/platform/x86.h>: Add LBR supportH.J. Lu2023-04-052-1/+2
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