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* <sys/platform/x86.h>: Add Intel LAM supportH.J. Lu2020-12-222-0/+4
* x86: Remove the default REP MOVSB threshold tunable value [BZ #27061]H.J. Lu2020-12-141-2/+4
* elf: Pass the fd to note processingSzabolcs Nagy2020-12-111-3/+3
* x86: Adjust tst-cpu-features-supports.c for GCC 11H.J. Lu2020-12-041-5/+10
* x86: Set RDRAND usable if CPU supports RDRANDH.J. Lu2020-12-041-0/+1
* x86: Remove UP macro. Define LOCK_PREFIX unconditionally.Florian Weimer2020-11-131-7/+1
* x86: Restore processing of cache size tunables in init_cacheinfoFlorian Weimer2020-10-281-8/+4
* x86: Optimizing memcpy for AMD Zen architecture.Sajan Karumanchi2020-10-281-6/+26
* x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu2020-10-167-857/+943
* <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM supportH.J. Lu2020-10-093-0/+18
* <sys/platform/x86.h>: Add Intel HRESET supportH.J. Lu2020-10-092-0/+4
* <sys/platform/x86.h>: Add AVX-VNNI supportH.J. Lu2020-10-093-0/+7
* <sys/platform/x86.h>: Add AVX512_FP16 supportH.J. Lu2020-10-093-3/+7
* <sys/platform/x86.h>: Add Intel UINTR supportH.J. Lu2020-10-092-3/+4
* Reversing calculation of __x86_shared_non_temporal_thresholdPatrick McGehearty2020-09-281-5/+11
* x86: Harden printf against non-normal long double values (bug 26649)Florian Weimer2020-09-223-0/+64
* x86: Use one ldbl2mpn.c file for both i386 and x86_64Florian Weimer2020-09-221-0/+120
* x86: Use HAS_CPU_FEATURE with IBT and SHSTK [BZ #26625]H.J. Lu2020-09-173-6/+4
* <sys/platform/x86.h>: Add Intel Key Locker supportH.J. Lu2020-09-163-3/+42
* x86: Install <sys/platform/x86.h> [BZ #26124]H.J. Lu2020-09-118-141/+654
* x86: Set CPU usable feature bits conservatively [BZ #26552]H.J. Lu2020-09-031-96/+47
* x86: Rename Intel CPU feature namesH.J. Lu2020-08-052-15/+15
* x86: Support usable check for all CPU featuresH.J. Lu2020-07-136-439/+561
* x86: Remove __ASSEMBLER__ check in init-arch.hH.J. Lu2020-07-111-5/+1
* x86: Remove the unused __x86_prefetchwH.J. Lu2020-07-112-16/+4
* rtld: Clean up PT_NOTE and add PT_GNU_PROPERTY handlingSzabolcs Nagy2020-07-081-40/+7
* x86: Add thresholds for "rep movsb/stosb" to tunablesH.J. Lu2020-07-064-0/+68
* x86: Detect Extended Feature Disable (XFD)H.J. Lu2020-07-062-0/+4
* x86: Correct bit_cpu_CLFSH [BZ #26208]H.J. Lu2020-07-061-1/+1
* x86: Detect Intel Advanced Matrix ExtensionsH.J. Lu2020-06-263-0/+44
* x86: Update CPU feature detection [BZ #26149]H.J. Lu2020-06-224-389/+267
* i386: Use builtin sqrtlAdhemerval Zanella2020-06-221-0/+27
* x86: Update F16C detection [BZ #26133]H.J. Lu2020-06-182-3/+7
* x86: Correct bit_cpu_CLFLUSHOPT [BZ #26128]H.J. Lu2020-06-171-1/+1
* x86: Update Intel Atom processor family optimizationH.J. Lu2020-05-211-1/+19
* x86: Add --enable-cet=permissiveH.J. Lu2020-05-186-43/+69
* x86: Move CET control to _dl_x86_feature_control [BZ #25887]H.J. Lu2020-05-186-66/+77
* semaphore: consolidate arch headers into a generic oneVineet Gupta2020-05-061-40/+0
* i386: Remove unused variable in sysdeps/x86/cacheinfo.cFlorian Weimer2020-04-301-1/+1
* x86: Add the test case of __get_cpu_features support for Zhaoxin processorsmayshao-oc2020-04-301-0/+2
* x86: Add cache information support for Zhaoxin processorsmayshao-oc2020-04-301-196/+282
* x86: Add CPU Vendor ID detection support for Zhaoxin processorsmayshao2020-04-302-0/+55
* Revert "x86_64: Add SSE sfp-exceptions"Adhemerval Zanella2020-04-201-57/+0
* x86_64: Add SSE sfp-exceptionsAdhemerval Zanella2020-04-171-0/+57
* x86: Remove feraiseexcept optimizationAdhemerval Zanella2020-03-302-111/+0
* x86: Remove ARCH_CET_LEGACY_BITMAP [BZ #25397]H.J. Lu2020-03-188-183/+165
* Introduce <elf-initfini.h> and ELF_INITFINI for all architecturesFlorian Weimer2020-02-181-0/+20
* x86: Remove <bits/select.h> and use the generic versionFlorian Weimer2020-02-091-63/+0
* x86: Don't make 2 calls to dlerror () in a rowH.J. Lu2020-02-012-2/+2
* Add libm_alias_finite for _finite symbolsWilco Dijkstra2020-01-031-1/+2
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