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* x86: Check RTM_ALWAYS_ABORT for RTM [BZ #28033]H.J. Lu2021-07-015-6/+11
* x86: Fix tst-cpu-features-cpuinfo on Ryzen 9 (BZ #27873)Adhemerval Zanella2021-06-243-4/+34
* x86: Copy IBT and SHSTK usable only if CET is enabledH.J. Lu2021-06-231-2/+5
* dlfcn: Cleanups after -ldl is no longer requiredFlorian Weimer2021-06-031-11/+2
* Properly check stack alignment [BZ #27901]H.J. Lu2021-05-241-0/+28
* x86: Set rep_movsb_threshold to 2112 on processors with FSRMH.J. Lu2021-05-031-0/+4
* x86: tst-cpu-features-supports.c: Update AMX checkH.J. Lu2021-04-221-3/+3
* nptl: Remove longjmp, siglongjmp from libpthreadFlorian Weimer2021-04-211-71/+0
* Move __isnanf128 to libc.soSiddhesh Poyarekar2021-03-301-0/+1
* x86: Add string/memory function tests in RTM regionH.J. Lu2021-03-2912-0/+618
* x86: Set Prefer_No_VZEROUPPER and add Prefer_AVX2_STRCMPH.J. Lu2021-03-293-2/+21
* x86: Properly disable XSAVE related features [BZ #27605]H.J. Lu2021-03-292-0/+56
* elf: Fix not compiling ifunc tests that need gcc ifunc supportSamuel Thibault2021-03-241-0/+2
* Build get-cpuid-feature-leaf.c without stack-protector [BZ #27555]Siddhesh Poyarekar2021-03-152-0/+4
* x86: Handle _SC_LEVEL1_ICACHE_LINESIZE [BZ #27444]H.J. Lu2021-03-157-0/+79
* x86: Set minimum x86-64 level marker [BZ #27318]H.J. Lu2021-03-063-11/+58
* x86: Add CPU-specific diagnostics to ld.so --list-diagnosticsFlorian Weimer2021-03-022-0/+120
* x86: Automate generation of PREFERRED_FEATURE_INDEX_1 bitfieldFlorian Weimer2021-03-022-34/+51
* x86: Use x86/nptl/pthreaddef.hH.J. Lu2021-02-221-0/+49
* x86: Remove unused variables for raw cache sizes from cacheinfo.hFlorian Weimer2021-02-221-12/+0
* <bits/platform/x86.h>: Correct x86_cpu_TBMH.J. Lu2021-02-221-1/+1
* x86: Remove the extra space between "# endif"H.J. Lu2021-02-121-1/+1
* x86: Use SIZE_MAX instead of (long int)-1 for tunable range valueSiddhesh Poyarekar2021-02-101-5/+5
* tunables: Simplify TUNABLE_SET interfaceSiddhesh Poyarekar2021-02-101-9/+6
* x86: Add PTWRITE feature detection [BZ #27346]H.J. Lu2021-02-079-5/+44
* x86: Adding an upper bound for Enhanced REP MOVSB.Sajan Karumanchi2021-02-023-1/+20
* sysconf: Add _SC_MINSIGSTKSZ/_SC_SIGSTKSZ [BZ #20305]H.J. Lu2021-02-012-0/+30
* x86: Properly set usable CET feature bits [BZ #26625]H.J. Lu2021-01-2910-13/+120
* Fix misplaced constAndreas Schwab2021-01-252-2/+2
* x86: Properly match CPU features in /proc/cpuinfo [BZ #27222]H.J. Lu2021-01-221-13/+30
* x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072]H.J. Lu2021-01-216-0/+184
* Use hidden visibility for early static PIE codeSzabolcs Nagy2021-01-211-0/+5
* <sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu2021-01-2112-832/+1153
* x86: Move x86 processor cache info to cpu_featuresH.J. Lu2021-01-145-412/+551
* Fix x86 build with --enable-tunable=noAdhemerval Zanella2021-01-141-0/+1
* ldconfig/x86: Store ISA level in cache and aux cacheH.J. Lu2021-01-131-0/+31
* x86: Set header.feature_1 in TCB for always-on CET [BZ #27177]H.J. Lu2021-01-133-1/+11
* x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]H.J. Lu2021-01-0717-41/+607
* Drop nan-pseudo-number.h usage from testsSiddhesh Poyarekar2021-01-041-1/+0
* Update copyright dates with scripts/update-copyrightsPaul Eggert2021-01-0281-81/+81
* x86 long double: Consider pseudo numbers as signalingSiddhesh Poyarekar2020-12-301-0/+30
* Remove _ISOMAC check from <cpu-features.h>H.J. Lu2020-12-241-81/+75
* x86: Remove the duplicated CPU_FEATURE_CPU_PH.J. Lu2020-12-241-2/+0
* Partially revert 681900d29683722b1cb0a8e565a0585846ec5a61Siddhesh Poyarekar2020-12-242-12/+1
* x86 long double: Support pseudo numbers in isnanlSiddhesh Poyarekar2020-12-241-0/+45
* x86 long double: Support pseudo numbers in fpclassifylSiddhesh Poyarekar2020-12-241-0/+46
* <sys/platform/x86.h>: Add Intel LAM supportH.J. Lu2020-12-222-0/+4
* x86: Remove the default REP MOVSB threshold tunable value [BZ #27061]H.J. Lu2020-12-141-2/+4
* elf: Pass the fd to note processingSzabolcs Nagy2020-12-111-3/+3
* x86: Adjust tst-cpu-features-supports.c for GCC 11H.J. Lu2020-12-041-5/+10
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