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* x86: Add PTWRITE feature detection [BZ #27346]H.J. Lu2021-02-071-0/+8
* sysconf: Add _SC_MINSIGSTKSZ/_SC_SIGSTKSZ [BZ #20305]H.J. Lu2021-02-011-0/+3
* x86: Properly set usable CET feature bits [BZ #26625]H.J. Lu2021-01-291-2/+9
* <sys/platform/x86.h>: Remove the C preprocessor magicH.J. Lu2021-01-211-34/+34
* x86: Move x86 processor cache info to cpu_featuresH.J. Lu2021-01-141-27/+8
* x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]H.J. Lu2021-01-071-0/+3
* Update copyright dates with scripts/update-copyrightsPaul Eggert2021-01-021-1/+1
* x86: Set RDRAND usable if CPU supports RDRANDH.J. Lu2020-12-041-0/+1
* x86: Initialize CPU info via IFUNC relocation [BZ 26203]H.J. Lu2020-10-161-1/+11
* <sys/platform/x86.h>: Add FSRCS/FSRS/FZLRM supportH.J. Lu2020-10-091-0/+3
* <sys/platform/x86.h>: Add AVX-VNNI supportH.J. Lu2020-10-091-0/+2
* <sys/platform/x86.h>: Add AVX512_FP16 supportH.J. Lu2020-10-091-0/+2
* x86: Use HAS_CPU_FEATURE with IBT and SHSTK [BZ #26625]H.J. Lu2020-09-171-2/+2
* <sys/platform/x86.h>: Add Intel Key Locker supportH.J. Lu2020-09-161-0/+14
* x86: Set CPU usable feature bits conservatively [BZ #26552]H.J. Lu2020-09-031-96/+47
* x86: Support usable check for all CPU featuresH.J. Lu2020-07-131-187/+249
* x86: Add thresholds for "rep movsb/stosb" to tunablesH.J. Lu2020-07-061-0/+4
* x86: Detect Intel Advanced Matrix ExtensionsH.J. Lu2020-06-261-0/+18
* x86: Update CPU feature detection [BZ #26149]H.J. Lu2020-06-221-68/+88
* x86: Update F16C detection [BZ #26133]H.J. Lu2020-06-181-0/+4
* x86: Update Intel Atom processor family optimizationH.J. Lu2020-05-211-1/+19
* x86: Move CET control to _dl_x86_feature_control [BZ #25887]H.J. Lu2020-05-181-7/+5
* x86: Add CPU Vendor ID detection support for Zhaoxin processorsmayshao2020-04-301-0/+54
* Update copyright dates with scripts/update-copyrights.Joseph Myers2020-01-011-1/+1
* Prefer https to http for gnu.org and fsf.org URLsPaul Eggert2019-09-071-1/+1
* Break more lines before not after operators.Joseph Myers2019-02-251-4/+4
* Add fall-through comments.Joseph Myers2019-02-121-0/+2
* Update copyright dates with scripts/update-copyrights.Joseph Myers2019-01-011-1/+1
* x86: Add Hygon Dhyana support.Carlos O'Donell2018-12-131-2/+3
* x86: Extend CPUID support in struct cpu_featuresH.J. Lu2018-12-031-34/+107
* x86: Fix Haswell strong flags (BZ#23709)Adhemerval Zanella2018-10-231-0/+6
* Rename the glibc.tune namespace to glibc.cpuSiddhesh Poyarekar2018-08-021-3/+3
* x86: Rename get_common_indeces to get_common_indicesH.J. Lu2018-08-011-4/+4
* x86: Populate COMMON_CPUID_INDEX_80000001 for Intel CPUs [BZ #23459]H.J. Lu2018-07-261-9/+18
* x86: Always include <dl-cet.h>/cet-tunables.h> for --enable-cetH.J. Lu2018-07-171-2/+5
* x86: Support IBT and SHSTK in Intel CET [BZ #21598]H.J. Lu2018-07-161-0/+60
* Use AVX_Fast_Unaligned_Load from Zen onwards.Amit Pawar2018-07-061-5/+13
* Update copyright dates with scripts/update-copyrights.Joseph Myers2018-01-011-1/+1
* x86-64: Use fxsave/xsave/xsavec in _dl_runtime_resolve [BZ #21265]H.J. Lu2017-10-201-17/+71
* x86-64: Don't set GLRO(dl_platform) to NULL [BZ #22299]H.J. Lu2017-10-191-4/+8
* x86: Add x86_64 to x86-64 HWCAP [BZ #22093]H.J. Lu2017-09-111-1/+2
* x86-64: Use _dl_runtime_resolve_opt only with AVX512F [BZ #21871]H.J. Lu2017-08-041-2/+5
* x86: Rename glibc.tune.ifunc to glibc.tune.hwcapsH.J. Lu2017-06-211-2/+2
* tunables: Add IFUNC selection and cache sizesH.J. Lu2017-06-201-0/+19
* Make LD_HWCAP_MASK usable for static binariesSiddhesh Poyarekar2017-06-071-5/+3
* tunables: Use glibc.tune.hwcap_mask tunable instead of _dl_hwcap_maskSiddhesh Poyarekar2017-06-071-0/+4
* x86: Set dl_platform and dl_hwcap from CPU features [BZ #21391]H.J. Lu2017-05-031-0/+48
* x86: Use AVX2 memcpy/memset on Skylake server [BZ #21396]H.J. Lu2017-04-181-1/+5
* x86: Set Prefer_No_VZEROUPPER if AVX512ER is availableH.J. Lu2017-04-181-2/+6
* Use CPU_FEATURES_CPU_P to check if AVX is availableH.J. Lu2017-03-171-2/+1
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