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* Update copyright dates with scripts/update-copyrightsPaul Eggert2024-01-011-1/+1
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* Update copyright dates with scripts/update-copyrightsJoseph Myers2023-01-061-1/+1
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* riscv: Remove RV32 floating point functionsAlistair Francis2022-09-214-124/+0
| | | | | | | We don't need RV32 specific floating point functions, instead make them generic for RISC-V. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
* riscv: Consolidate the libm-test-ulpsAlistair Francis2022-09-212-1406/+0
| | | | | | | Both RV32 and RV64 should have the same libm-test-ulps, so consolidate them into a single file. Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
* manual: Avoid name collision in libm ULP table [BZ #28956]Tom Coldrick2022-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The 32-bit and 64-bit variants of RISC-V share the same name - "RISC-V" - when generating the libm error table for the info pages. This collision, and the way how the table is generated, mean that the values in the final table for "RISC-V" may be either for the 32- or 64-bit variant, with no indication as to which. As an additional side-effect, this makes the build non-reproducible, as the error table generated is dependent upon the host filesystem implementation. To solve this issue, the libm-test-ulps-name files for both variants have been modified to include their word size, so as to remove the collision and provide more accurate information in the table. An alternative proposed was to merge the two variants' ULP values into a single file, but this would mean that information about error values is lost, as the two variants are not identical. Some differences are considerable, notably the values for the exp() function are large. Reviewed-by: Carlos O'Donell <carlos@redhat.com> Tested-by: Carlos O'Donell <carlos@redhat.com>
* Update copyright dates with scripts/update-copyrightsPaul Eggert2022-01-015-5/+5
| | | | | | | | | | | | | | | | | | | | | | | I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 7061 files FOO. I then removed trailing white space from math/tgmath.h, support/tst-support-open-dev-null-range.c, and sysdeps/x86_64/multiarch/strlen-vec.S, to work around the following obscure pre-commit check failure diagnostics from Savannah. I don't know why I run into these diagnostics whereas others evidently do not. remote: *** 912-#endif remote: *** 913: remote: *** 914- remote: *** error: lines with trailing whitespace found ... remote: *** error: sysdeps/unix/sysv/linux/statx_cp.c: trailing lines
* Update copyright dates with scripts/update-copyrightsPaul Eggert2021-01-025-5/+5
| | | | | | | | | | | | | | | | I used these shell commands: ../glibc/scripts/update-copyrights $PWD/../gnulib/build-aux/update-copyright (cd ../glibc && git commit -am"[this commit message]") and then ignored the output, which consisted lines saying "FOO: warning: copyright statement not found" for each of 6694 files FOO. I then removed trailing white space from benchtests/bench-pthread-locks.c and iconvdata/tst-iconv-big5-hkscs-to-2ucs4.c, to work around this diagnostic from Savannah: remote: *** pre-commit check failed ... remote: *** error: lines with trailing whitespace found remote: error: hook declined to update refs/heads/master
* RISC-V: Build infrastructure for 32-bit portZong Li2020-08-273-0/+5
| | | | | | | | This patch lays out the top-level organisation of the RISC-V 32-bit port. It provides all the Implies files as well as various other fragments of the build infrastructure. Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
* RISC-V: Fix llrint and llround missing exceptions on RV32Zong Li2020-08-271-0/+38
| | | | | | | | | Conversions from a float to a long long on 32-bit RISC-V (RV32) may not raise the correct exceptions on overflow, it also may raise spurious "inexact" exceptions on non overflow cases. This patch fixes the problem, similarly to the fix for MIPS, ARM and S390. Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
* RISC-V: Add the RV32 libm-test-ulpsAlistair Francis2020-08-272-0/+1406
| | | | | | | | | Add a libm-test-ulps for RV32, this is the same as the RV64 one. This dosn't match what is generated by running `make regen-ulps` on RV32 QEMU, but the current in tree RV64 doesn't match that either. Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
* RISC-V: Add hard float support for 32-bit CPUsZong Li2020-08-274-0/+124
This patch adds support for hardware floating-point support for the RV32IF and RV32IFD platforms. Reviewed-by: Maciej W. Rozycki <macro@wdc.com>