| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Update copyright dates with scripts/update-copyrights | Paul Eggert | 2024-01-01 | 1 | -1/+1 |
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| * | aarch64: Add half-width versions of AdvSIMD f32 libmvec routines | Joe Ramsay | 2023-12-20 | 1 | -1/+3 |
| | | | | | | | | | | | | Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com> | ||||
| * | aarch64: Add vector implementations of exp routines | Joe Ramsay | 2023-06-30 | 1 | -0/+133 |
| Optimised implementations for single and double precision, Advanced SIMD and SVE, copied from Arm Optimized Routines. As previously, data tables are used via a barrier to prevent overly aggressive constant inlining. Special-case handlers are marked NOINLINE to avoid incurring the penalty of switching call standards unnecessarily. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com> | |||||
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index : mirror/glibc | |
| mirror of git://sourceware.org/git/glibc.git | Leah Neukirchen |
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