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Add Fast Short REP CMP and SCA (FSRCS), Fast Short REP STO (FSRS) and
Fast Zero-Length REP MOV (FZLRM) support to <sys/platform/x86.h>.
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Add Intel HRESET support to <sys/platform/x86.h>.
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Add AVX-VNNI support to <sys/platform/x86.h>.
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Add AVX512_FP16 support to <sys/platform/x86.h>.
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Add Intel UINTR support to <sys/platform/x86.h>.
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Add Intel Key Locker:
https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html
support to <sys/platform/x86.h>. Intel Key Locker has
1. KL: AES Key Locker instructions.
2. WIDE_KL: AES wide Key Locker instructions.
3. AESKLE: AES Key Locker instructions are enabled by OS.
Applications should use
if (CPU_FEATURE_USABLE (KL))
and
if (CPU_FEATURE_USABLE (WIDE_KL))
to check if AES Key Locker instructions and AES wide Key Locker
instructions are usable.
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Install <sys/platform/x86.h> so that programmers can do
#if __has_include(<sys/platform/x86.h>)
#include <sys/platform/x86.h>
#endif
...
if (CPU_FEATURE_USABLE (SSE2))
...
if (CPU_FEATURE_USABLE (AVX2))
...
<sys/platform/x86.h> exports only:
enum
{
COMMON_CPUID_INDEX_1 = 0,
COMMON_CPUID_INDEX_7,
COMMON_CPUID_INDEX_80000001,
COMMON_CPUID_INDEX_D_ECX_1,
COMMON_CPUID_INDEX_80000007,
COMMON_CPUID_INDEX_80000008,
COMMON_CPUID_INDEX_7_ECX_1,
/* Keep the following line at the end. */
COMMON_CPUID_INDEX_MAX
};
struct cpuid_features
{
struct cpuid_registers cpuid;
struct cpuid_registers usable;
};
struct cpu_features
{
struct cpu_features_basic basic;
struct cpuid_features features[COMMON_CPUID_INDEX_MAX];
};
/* Get a pointer to the CPU features structure. */
extern const struct cpu_features *__x86_get_cpu_features
(unsigned int max) __attribute__ ((const));
Since all feature checks are done through macros, programs compiled with
a newer <sys/platform/x86.h> are compatible with the older glibc binaries
as long as the layout of struct cpu_features is identical. The features
array can be expanded with backward binary compatibility for both .o and
.so files. When COMMON_CPUID_INDEX_MAX is increased to support new
processor features, __x86_get_cpu_features in the older glibc binaries
returns NULL and HAS_CPU_FEATURE/CPU_FEATURE_USABLE return false on the
new processor feature. No new symbol version is neeeded.
Both CPU_FEATURE_USABLE and HAS_CPU_FEATURE are provided. HAS_CPU_FEATURE
can be used to identify processor features.
Note: Although GCC has __builtin_cpu_supports, it only supports a subset
of <sys/platform/x86.h> and it is equivalent to CPU_FEATURE_USABLE. It
doesn't support HAS_CPU_FEATURE.
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The opening parenthesis for function arguments in an @deftypefun need
to be separated from the function name. This isn't just a matter of
the GNU coding style---it causes the "(void" (in this case) to be
rendered as a part of the function name, causing a visual defect, and
also results in a warning to the following effect during `make pdf':
Warning: unbalanced parentheses in @def...)
* manual/platform.texi (__riscv_flush_icache): Fix @deftypefun
syntax.
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This function is used by GCC to enforce ordering between data writes and
instruction fetches, and while we'd prefer that users rely on the GCC
intrinsic when possible this is user visible in case that's not
possible.
2018-01-29 Palmer Dabbelt <palmer@sifive.com>
* manual/platform.texi: Add RISC-V documenation for
__riscv_flush_icache.
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This patch adds extra inline functions to change the Program Priority
Register from ISA 2.07.
2015-08-19 Gabriel F. T. Gomes <gftg@linux.vnet.ibm.com>
* sysdeps/powerpc/sys/platform/ppc.h (__ppc_set_ppr_med_high,
__ppc_set_ppr_very_low): New functions.
* manual/platform.texi: Add documentation about
__ppc_set_ppr_med_high and __ppc_set_ppr_very_low.
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Fixup for commit d116b7c414c8239b677e341ac517745db689ac2d.
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This patch add inline functions to change the Program Priority Register
from ISA 2.05.
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[BZ #13743]
A new class of installed headers has been documented for low-level
platform-specific functionality. PowerPC added the first instance with a
function to provide time base register access (__ppc_get_timebase). This
is required for applications that measure time at high frequencies with
high precision that can't afford a syscall.
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