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| author | H.J. Lu <hjl.tools@gmail.com> | 2020-10-08 08:19:15 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2020-10-09 11:52:30 -0700 |
| commit | 7674695cf7e28528be7243ceb30c9a600bbaa7b5 (patch) | |
| tree | 4cac579b2110239b2adcf0336b6fb760c92644cc /manual/platform.texi | |
| parent | bb5fd5ce64b598085bdb8a05cb53777480fe093c (diff) | |
| download | glibc-7674695cf7e28528be7243ceb30c9a600bbaa7b5.tar.gz glibc-7674695cf7e28528be7243ceb30c9a600bbaa7b5.tar.xz glibc-7674695cf7e28528be7243ceb30c9a600bbaa7b5.zip | |
<sys/platform/x86.h>: Add Intel UINTR support
Add Intel UINTR support to <sys/platform/x86.h>.
Diffstat (limited to 'manual/platform.texi')
| -rw-r--r-- | manual/platform.texi | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/manual/platform.texi b/manual/platform.texi index 95b0ed0642..0dd12a4353 100644 --- a/manual/platform.texi +++ b/manual/platform.texi @@ -584,6 +584,9 @@ using a TSC deadline value. @code{TSXLDTRK} -- TSXLDTRK instructions. @item +@code{UINTR} -- User interrupts. + +@item @code{UMIP} -- User-mode instruction prevention. @item |