diff options
| -rw-r--r-- | ChangeLog | 10 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strcspn.S | 6 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strlen.S | 4 | ||||
| -rw-r--r-- | sysdeps/i386/i686/multiarch/strspn.S | 6 | ||||
| -rw-r--r-- | sysdeps/x86_64/multiarch/init-arch.h | 2 |
5 files changed, 20 insertions, 8 deletions
diff --git a/ChangeLog b/ChangeLog index 45b9d2d42d..ce4d4e8e3b 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,13 @@ +2009-12-13 H.J. Lu <hongjiu.lu@intel.com> + + * sysdeps/i386/i686/multiarch/strcspn.S Include <init-arch.h> + instead of <ifunc-defines.h>. Use bit_XXX and index_XXX to + check processor feature. + * sysdeps/i386/i686/multiarch/strlen.S: Likewise. + * sysdeps/i386/i686/multiarch/strspn.S: Likewise. + * sysdeps/x86_64/multiarch/init-arch.h (bit_SSE2): New definition. + (index_SSE2): Likewise. + 2009-12-09 H.J. Lu <hongjiu.lu@intel.com> * sysdeps/x86_64/multiarch/init-arch.h: Include <ifunc-defines.h> diff --git a/sysdeps/i386/i686/multiarch/strcspn.S b/sysdeps/i386/i686/multiarch/strcspn.S index 73e7eb45a8..b2310e4a8b 100644 --- a/sysdeps/i386/i686/multiarch/strcspn.S +++ b/sysdeps/i386/i686/multiarch/strcspn.S @@ -23,7 +23,7 @@ #ifdef HAVE_SSE4_SUPPORT #include <sysdep.h> -#include <ifunc-defines.h> +#include <init-arch.h> #ifdef USE_AS_STRPBRK #define STRCSPN_SSE42 __strpbrk_sse42 @@ -64,7 +64,7 @@ ENTRY(STRCSPN) jne 1f call __init_cpu_features 1: leal STRCSPN_IA32@GOTOFF(%ebx), %eax - testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx) + testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f leal STRCSPN_SSE42@GOTOFF(%ebx), %eax 2: popl %ebx @@ -80,7 +80,7 @@ ENTRY(STRCSPN) jne 1f call __init_cpu_features 1: leal STRCSPN_IA32, %eax - testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features + testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f leal STRCSPN_SSE42, %eax 2: ret diff --git a/sysdeps/i386/i686/multiarch/strlen.S b/sysdeps/i386/i686/multiarch/strlen.S index 0c1e8646ff..9786add745 100644 --- a/sysdeps/i386/i686/multiarch/strlen.S +++ b/sysdeps/i386/i686/multiarch/strlen.S @@ -19,7 +19,7 @@ 02111-1307 USA. */ #include <sysdep.h> -#include <ifunc-defines.h> +#include <init-arch.h> /* Define multiple versions only for the definition in libc and for the DSO. In static binaries, we need strlen before the initialization @@ -46,7 +46,7 @@ ENTRY(strlen) jne 1f call __init_cpu_features 1: leal __strlen_ia32@GOTOFF(%ebx), %eax - testl $(1<<26), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET+__cpu_features@GOTOFF(%ebx) + testl $bit_SSE2, CPUID_OFFSET+index_SSE2+__cpu_features@GOTOFF(%ebx) jz 2f leal __strlen_sse2@GOTOFF(%ebx), %eax 2: popl %ebx diff --git a/sysdeps/i386/i686/multiarch/strspn.S b/sysdeps/i386/i686/multiarch/strspn.S index f306d2d1fb..7fe6f97f41 100644 --- a/sysdeps/i386/i686/multiarch/strspn.S +++ b/sysdeps/i386/i686/multiarch/strspn.S @@ -23,7 +23,7 @@ #ifdef HAVE_SSE4_SUPPORT #include <sysdep.h> -#include <ifunc-defines.h> +#include <init-arch.h> /* Define multiple versions only for the definition in libc. */ #ifndef NOT_IN_libc @@ -49,7 +49,7 @@ ENTRY(strspn) jne 1f call __init_cpu_features 1: leal __strspn_ia32@GOTOFF(%ebx), %eax - testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features@GOTOFF(%ebx) + testl $bit_SSE4_2, CPUID_OFFSET+index_SSE4_2+__cpu_features@GOTOFF(%ebx) jz 2f leal __strspn_sse42@GOTOFF(%ebx), %eax 2: popl %ebx @@ -65,7 +65,7 @@ ENTRY(strspn) jne 1f call __init_cpu_features 1: leal __strspn_ia32, %eax - testl $(1<<20), CPUID_OFFSET+COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET+__cpu_features + testl $index_SSE2, CPUID_OFFSET+index_SSE4_2+__cpu_features jz 2f leal __strspn_sse42, %eax 2: ret diff --git a/sysdeps/x86_64/multiarch/init-arch.h b/sysdeps/x86_64/multiarch/init-arch.h index 9e8915fa40..0f8f77a8a1 100644 --- a/sysdeps/x86_64/multiarch/init-arch.h +++ b/sysdeps/x86_64/multiarch/init-arch.h @@ -20,9 +20,11 @@ #include <ifunc-defines.h> +#define bit_SSE2 (1 << 26) #define bit_SSSE3 (1 << 9) #define bit_SSE4_2 (1 << 20) +#define index_SSE2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_EDX_OFFSET #define index_SSSE3 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET #define index_SSE4_2 COMMON_CPUID_INDEX_1*CPUID_SIZE+CPUID_ECX_OFFSET |