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author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-12-19 16:44:01 +0000 |
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committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-12-20 08:41:25 +0000 |
commit | cc0d77ba944cd4ce46c5f0e6d426af3057962ca5 (patch) | |
tree | 840c09b10bcb0ad4f733e8cb4bce2acbd92e5945 /wctype | |
parent | 3150cc0c9019bf9da841419f86dda8e7f26d676d (diff) | |
download | glibc-cc0d77ba944cd4ce46c5f0e6d426af3057962ca5.tar.gz glibc-cc0d77ba944cd4ce46c5f0e6d426af3057962ca5.tar.xz glibc-cc0d77ba944cd4ce46c5f0e6d426af3057962ca5.zip |
aarch64: Add half-width versions of AdvSIMD f32 libmvec routines
Compilers may emit calls to 'half-width' routines (two-lane single-precision variants). These have been added in the form of wrappers around the full-width versions, where the low half of the vector is simply duplicated. This will perform poorly when one lane triggers the special-case handler, as there will be a redundant call to the scalar version, however this is expected to be rare at Ofast. Reviewed-by: Szabolcs Nagy <szabolcs.nagy@arm.com>
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