diff options
author | mengqinggang <mengqinggang@loongson.cn> | 2024-06-21 16:08:53 +0800 |
---|---|---|
committer | caiyinyu <caiyinyu@loongson.cn> | 2024-06-26 12:02:07 +0800 |
commit | a10b6ad471d7b528149f5ff32eef2f1c1dc1213c (patch) | |
tree | 12657d43fabece5866ed99b0302f144b31c19648 /wcsmbs/test-c8rtomb.c | |
parent | c90cfce849d010474e8cccf3e5bff49a2c8b141f (diff) | |
download | glibc-a10b6ad471d7b528149f5ff32eef2f1c1dc1213c.tar.gz glibc-a10b6ad471d7b528149f5ff32eef2f1c1dc1213c.tar.xz glibc-a10b6ad471d7b528149f5ff32eef2f1c1dc1213c.zip |
LoongArch: Fix tst-gnu2-tls2 test case
asm volatile ("movfcsr2gr $t0, $fcsr0" ::: "$t0"); asm volatile ("st.d $t0, %0" :"=m"(restore_fcsr)); generate to the following instructions with -Og flag: movfcsr2gr $t0, $zero addi.d $t0, $sp, 2047(0x7ff) addi.d $t0, $t0, 77(0x4d) st.w $t0, $t0, 0 fcsr0 register and restore_fcsr variable are both stored in t0 register. Change to: asm volatile ("movfcsr2gr %0, $fcsr0" :"=r"(restore_fcsr)); to avoid restore_fcsr address in t0. Comparing float value using memcmp because float value cannot be directly compared for equality. Put LOAD_REGISTER_FCSR and SAVE_REGISTER_FCC after LOAD_REGISTER_FLOAT. Some float instructions may change fcsr register.
Diffstat (limited to 'wcsmbs/test-c8rtomb.c')
0 files changed, 0 insertions, 0 deletions