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authorH.J. Lu <hongjiu.lu@intel.com>2011-06-03 07:01:25 -0400
committerUlrich Drepper <drepper@gmail.com>2011-06-03 07:01:25 -0400
commit3d29045b5e8329d97693eda8d98f1d1e60b99c8f (patch)
treeed61b7ed0c25b443d9ff47fa0f2d79c562ca6cc2 /sysdeps/x86_64/multiarch
parentc8fc0c91695b1c7003c7170861274161f9224817 (diff)
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Assume Intel Core i3/i5/i7 processor if AVX is available
Diffstat (limited to 'sysdeps/x86_64/multiarch')
-rw-r--r--sysdeps/x86_64/multiarch/init-arch.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/sysdeps/x86_64/multiarch/init-arch.c b/sysdeps/x86_64/multiarch/init-arch.c
index 34ec2df2d5..809d105c77 100644
--- a/sysdeps/x86_64/multiarch/init-arch.c
+++ b/sysdeps/x86_64/multiarch/init-arch.c
@@ -74,6 +74,7 @@ __init_cpu_features (void)
 	}
       else if (family == 0x06)
 	{
+	  ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
 	  model += extended_model;
 	  switch (model)
 	    {
@@ -83,6 +84,12 @@ __init_cpu_features (void)
 	      __cpu_features.feature[index_Slow_BSF] |= bit_Slow_BSF;
 	      break;
 
+	    default:
+	      /* Unknown family 0x06 processors.  Assuming this is one
+	         of Core i3/i5/i7 processors if AVX is available.  */
+	      if ((ecx & bit_AVX) == 0)
+		break;
+
 	    case 0x1a:
 	    case 0x1e:
 	    case 0x1f: