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| author | Noah Goldstein <goldstein.w.n@gmail.com> | 2022-06-09 11:16:36 -0700 |
|---|---|---|
| committer | Noah Goldstein <goldstein.w.n@gmail.com> | 2022-06-09 12:51:22 -0700 |
| commit | bcc41f66a48bf764ee85fea56b8e32719e230a0a (patch) | |
| tree | 227a84a2baf472eac75532ef4c10ec4bf884dae7 /sysdeps/x86_64/fpu/multiarch/svml_s_tanhf4_core_sse4.S | |
| parent | 3a49ce8799e7233946f8154ba05c185277f33f11 (diff) | |
| download | glibc-bcc41f66a48bf764ee85fea56b8e32719e230a0a.tar.gz glibc-bcc41f66a48bf764ee85fea56b8e32719e230a0a.tar.xz glibc-bcc41f66a48bf764ee85fea56b8e32719e230a0a.zip | |
x86: Optimize svml_s_tanhf8_core_avx2.S
Optimizations are:
1. Reduce code size (-81 bytes).
2. Remove redundant move instructions.
3. Slightly improve instruction selection/scheduling where
possible.
4. Prefer registers which get short instruction encoding.
5. Reduce rodata size (-32 bytes).
Result is roughly a 17-18% speedup:
Function, New Time, Old Time, New / Old
_ZGVdN8v_tanhf, 1.977, 2.402, 0.823
Diffstat (limited to 'sysdeps/x86_64/fpu/multiarch/svml_s_tanhf4_core_sse4.S')
0 files changed, 0 insertions, 0 deletions