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| author | H.J. Lu <hjl.tools@gmail.com> | 2021-08-20 06:42:24 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2021-08-22 06:23:37 -0700 |
| commit | 78c9ec9000f873abe7a15a91b87080a2e4308260 (patch) | |
| tree | 1fb85aec1d1f6394f650758f5074130e77fea131 /sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S | |
| parent | c333dcf8d8f9e6e46475d9eff24bd5394b5d3d9e (diff) | |
| download | glibc-78c9ec9000f873abe7a15a91b87080a2e4308260.tar.gz glibc-78c9ec9000f873abe7a15a91b87080a2e4308260.tar.xz glibc-78c9ec9000f873abe7a15a91b87080a2e4308260.zip | |
x86-64: Optimize load of all bits set into ZMM register [BZ #28252]
Optimize loads of all bits set into ZMM register in AVX512 SVML codes by replacing vpbroadcastq .L_2il0floatpacket.16(%rip), %zmmX and vmovups .L_2il0floatpacket.13(%rip), %zmmX with vpternlogd $0xff, %zmmX, %zmmX, %zmmX This fixes BZ #28252.
Diffstat (limited to 'sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S')
| -rw-r--r-- | sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S index be8ab7c6e0..48d251db16 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S @@ -261,7 +261,7 @@ WRAPPER_IMPL_AVX512 _ZGVdN4v_sin andq $-64, %rsp subq $1280, %rsp movq __svml_d_trig_data@GOTPCREL(%rip), %rax - vpbroadcastq .L_2il0floatpacket.14(%rip), %zmm14 + vpternlogd $0xff, %zmm1, %zmm1, %zmm14 vmovups __dAbsMask(%rax), %zmm7 vmovups __dInvPI(%rax), %zmm2 vmovups __dRShifter(%rax), %zmm1 @@ -458,8 +458,3 @@ WRAPPER_IMPL_AVX512 _ZGVdN4v_sin jmp .LBL_2_7 #endif END (_ZGVeN8v_sin_skx) - - .section .rodata, "a" -.L_2il0floatpacket.14: - .long 0xffffffff,0xffffffff - .type .L_2il0floatpacket.14,@object |