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| author | H.J. Lu <hjl.tools@gmail.com> | 2015-03-31 13:17:51 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2015-03-31 13:18:10 -0700 |
| commit | a3d9ab5070b56b49aa91be2887fa5b118012b2cd (patch) | |
| tree | 4352143efb08c51ec9cb480489e847de724afb06 /sysdeps/x86_64/cacheinfo.c | |
| parent | 83569fb894050db7430047da2219ca50c68f882a (diff) | |
| download | glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar.gz glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.tar.xz glibc-a3d9ab5070b56b49aa91be2887fa5b118012b2cd.zip | |
Limit threads sharing L2 cache to 2 for SLM/KNL
Silvermont and Knights Landing have a modular system design with two cores sharing an L2 cache. If more than 2 cores are detected to shared L2 cache, it should be adjusted for Silvermont and Knights Landing. [BZ #18185] * sysdeps/x86_64/cacheinfo.c (init_cacheinfo): Limit threads sharing L2 cache to 2 for Silvermont/Knights Landing.
Diffstat (limited to 'sysdeps/x86_64/cacheinfo.c')
| -rw-r--r-- | sysdeps/x86_64/cacheinfo.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/sysdeps/x86_64/cacheinfo.c b/sysdeps/x86_64/cacheinfo.c index f1cbf50957..b99fb9a762 100644 --- a/sysdeps/x86_64/cacheinfo.c +++ b/sysdeps/x86_64/cacheinfo.c @@ -585,6 +585,10 @@ init_cacheinfo (void) __cpuid (1, eax, ebx_1, ecx, edx); #endif + unsigned int family = (eax >> 8) & 0x0f; + unsigned int model = (eax >> 4) & 0x0f; + unsigned int extended_model = (eax >> 12) & 0xf0; + #ifndef DISABLE_PREFERRED_MEMORY_INSTRUCTION /* Intel prefers SSSE3 instructions for memory/string routines if they are available. */ @@ -647,6 +651,25 @@ init_cacheinfo (void) } } threads += 1; + if (threads > 2 && level == 2 && family == 6) + { + model += extended_model; + switch (model) + { + case 0x57: + /* Knights Landing has L2 cache shared by 2 cores. */ + case 0x37: + case 0x4a: + case 0x4d: + case 0x5a: + case 0x5d: + /* Silvermont has L2 cache shared by 2 cores. */ + threads = 2; + break; + default: + break; + } + } } else { |