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| author | Sajan Karumanchi <sajan.karumanchi@amd.com> | 2021-02-02 12:42:14 +0100 |
|---|---|---|
| committer | Florian Weimer <fweimer@redhat.com> | 2021-02-02 12:42:15 +0100 |
| commit | 6e02b3e9327b7dbb063958d2b124b64fcb4bbe3f (patch) | |
| tree | f5fa119e5c2db62c16cdbaaa01d856da390e607a /sysdeps/x86/include/cpu-features.h | |
| parent | caa60b79f8c98e97455078542a14b4c750e48ede (diff) | |
| download | glibc-6e02b3e9327b7dbb063958d2b124b64fcb4bbe3f.tar.gz glibc-6e02b3e9327b7dbb063958d2b124b64fcb4bbe3f.tar.xz glibc-6e02b3e9327b7dbb063958d2b124b64fcb4bbe3f.zip | |
x86: Adding an upper bound for Enhanced REP MOVSB.
In the process of optimizing memcpy for AMD machines, we have found the vector move operations are outperforming enhanced REP MOVSB for data transfers above the L2 cache size on Zen3 architectures. To handle this use case, we are adding an upper bound parameter on enhanced REP MOVSB:'__x86_rep_movsb_stop_threshold'. As per large-bench results, we are configuring this parameter to the L2 cache size for AMD machines and applicable from Zen3 architecture supporting the ERMS feature. For architectures other than AMD, it is the computed value of non-temporal threshold parameter. Reviewed-by: Premachandra Mallappa <premachandra.mallappa@amd.com>
Diffstat (limited to 'sysdeps/x86/include/cpu-features.h')
| -rw-r--r-- | sysdeps/x86/include/cpu-features.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sysdeps/x86/include/cpu-features.h b/sysdeps/x86/include/cpu-features.h index 624736b40e..475e877294 100644 --- a/sysdeps/x86/include/cpu-features.h +++ b/sysdeps/x86/include/cpu-features.h @@ -870,6 +870,8 @@ struct cpu_features unsigned long int non_temporal_threshold; /* Threshold to use "rep movsb". */ unsigned long int rep_movsb_threshold; + /* Threshold to stop using "rep movsb". */ + unsigned long int rep_movsb_stop_threshold; /* Threshold to use "rep stosb". */ unsigned long int rep_stosb_threshold; /* _SC_LEVEL1_ICACHE_SIZE. */ |