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author | Noah Goldstein <goldstein.w.n@gmail.com> | 2024-08-14 14:37:31 +0800 |
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committer | H.J. Lu <hjl.tools@gmail.com> | 2024-08-15 08:19:15 -0700 |
commit | f446d90fe6605ac473aaa6cd17a1800e72dcc1a2 (patch) | |
tree | a381ddf487e56995f35208f093ddacd49256da73 /sysdeps/x86/cpu-features.c | |
parent | b93dddfaf440aa12f45d7c356f6ffe9f27d35577 (diff) | |
download | glibc-f446d90fe6605ac473aaa6cd17a1800e72dcc1a2.tar.gz glibc-f446d90fe6605ac473aaa6cd17a1800e72dcc1a2.tar.xz glibc-f446d90fe6605ac473aaa6cd17a1800e72dcc1a2.zip |
x86: Add `Avoid_STOSB` tunable to allow NT memset without ERMS
The goal of this flag is to allow targets which don't prefer/have ERMS to still access the non-temporal memset implementation. There are 4 cases for tuning memset: 1) `Avoid_STOSB && Avoid_Non_Temporal_Memset` - Memset with temporal stores 2) `Avoid_STOSB && !Avoid_Non_Temporal_Memset` - Memset with temporal/non-temporal stores. Non-temporal path goes through `rep stosb` path. We accomplish this by setting `x86_rep_stosb_threshold` to `x86_memset_non_temporal_threshold`. 3) `!Avoid_STOSB && Avoid_Non_Temporal_Memset` - Memset with temporal stores/`rep stosb` 3) `!Avoid_STOSB && !Avoid_Non_Temporal_Memset` - Memset with temporal stores/`rep stosb`/non-temporal stores. Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
Diffstat (limited to 'sysdeps/x86/cpu-features.c')
-rw-r--r-- | sysdeps/x86/cpu-features.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c index a4786d23c7..0fb50f9432 100644 --- a/sysdeps/x86/cpu-features.c +++ b/sysdeps/x86/cpu-features.c @@ -1119,6 +1119,10 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht if (CPU_FEATURES_CPU_P (cpu_features, CMOV)) cpu_features->preferred[index_arch_I686] |= bit_arch_I686; + /* No ERMS, we want to avoid stosb for memset. */ + if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)) + cpu_features->preferred[index_arch_Avoid_STOSB] |= bit_arch_Avoid_STOSB; + #if !HAS_CPUID no_cpuid: #endif |