Remove trailing whitespace.

1 files changed, 20 insertions, 20 deletions

diff --git a/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h b/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
index 93580653a5..935a68c70a 100644
--- a/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
+++ b/sysdeps/unix/sysv/linux/powerpc/sys/ucontext.h
@@ -61,14 +61,14 @@ typedef struct
 
 #else
 
-/* For 64-bit kernels with Altivec support, a machine context is exactly 
- * a sigcontext.  For older kernel (without Altivec) the sigcontext matches 
- * the mcontext upto but not including the v_regs field.  For kernels that 
- * don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the 
+/* For 64-bit kernels with Altivec support, a machine context is exactly
+ * a sigcontext.  For older kernel (without Altivec) the sigcontext matches
+ * the mcontext upto but not including the v_regs field.  For kernels that
+ * don't AT_HWCAP or return AT_HWCAP without PPC_FEATURE_HAS_ALTIVEC the
  * v_regs field may not exit and should not be referenced.  The v_regd field
  * can be refernced safely only after verifying that PPC_FEATURE_HAS_ALTIVEC
  * is set in AT_HWCAP.  */
-    
+
 /* Number of general registers.  */
 # define NGREG	48	/* includes r0-r31, nip, msr, lr, etc.   */
 # define NFPREG	33	/* includes fp0-fp31 &fpscr.  */
@@ -78,7 +78,7 @@ typedef unsigned long gregset_t[NGREG];
 typedef double fpregset_t[NFPREG];
 
 /* Container for Altivec/VMX Vector Status and Control Register.  Only 32-bits
-   but can only be copied to/from a 128-bit vector register.  So we allocated 
+   but can only be copied to/from a 128-bit vector register.  So we allocated
    a whole quadword speedup save/restore.  */
 typedef struct _libc_vscr
 {
@@ -106,22 +106,22 @@ typedef struct {
 	gregset_t	gp_regs;
 	fpregset_t	fp_regs;
 /*
- * To maintain compatibility with current implementations the sigcontext is 
- * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t) 
- * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This 
- * allows the array of vector registers to be quadword aligned independent of 
- * the alignment of the containing sigcontext or ucontext. It is the 
- * responsibility of the code setting the sigcontext to set this pointer to 
- * either NULL (if this processor does not support the VMX feature) or the 
+ * To maintain compatibility with current implementations the sigcontext is
+ * extended by appending a pointer (v_regs) to a quadword type (elf_vrreg_t)
+ * followed by an unstructured (vmx_reserve) field of 69 doublewords.  This
+ * allows the array of vector registers to be quadword aligned independent of
+ * the alignment of the containing sigcontext or ucontext. It is the
+ * responsibility of the code setting the sigcontext to set this pointer to
+ * either NULL (if this processor does not support the VMX feature) or the
  * address of the first quadword within the allocated (vmx_reserve) area.
  *
- * The pointer (v_regs) of vector type (elf_vrreg_t) is essentually  
- * an array of 34 quadword entries.  The entries with 
- * indexes 0-31 contain the corresponding vector registers.  The entry with 
- * index 32 contains the vscr as the last word (offset 12) within the 
- * quadword.  This allows the vscr to be stored as either a quadword (since 
- * it must be copied via a vector register to/from storage) or as a word.  
- * The entry with index 33 contains the vrsave as the first word (offset 0) 
+ * The pointer (v_regs) of vector type (elf_vrreg_t) is essentually
+ * an array of 34 quadword entries.  The entries with
+ * indexes 0-31 contain the corresponding vector registers.  The entry with
+ * index 32 contains the vscr as the last word (offset 12) within the
+ * quadword.  This allows the vscr to be stored as either a quadword (since
+ * it must be copied via a vector register to/from storage) or as a word.
+ * The entry with index 33 contains the vrsave as the first word (offset 0)
  * within the quadword.
  */
 	vrregset_t	*v_regs;