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| author | Gordana Cmiljanovic <Gordana.Cmiljanovic@imgtec.com> | 2017-06-13 21:34:45 +0000 |
|---|---|---|
| committer | Joseph Myers <joseph@codesourcery.com> | 2017-06-13 21:34:45 +0000 |
| commit | b309f058cf7639951bebb86270ffbc116ea5f720 (patch) | |
| tree | bd42dec0d4649a94e18384bf0294f3c473a6aa83 /sysdeps/unix/sysv/linux/mips/setcontext.S | |
| parent | c2528fef3b05bcffb1ac27c6c09cc3ff24b7f03f (diff) | |
| download | glibc-b309f058cf7639951bebb86270ffbc116ea5f720.tar.gz glibc-b309f058cf7639951bebb86270ffbc116ea5f720.tar.xz glibc-b309f058cf7639951bebb86270ffbc116ea5f720.zip | |
mips: Fix store/load gp registers to/from ucontext_t
General purpose registers in mcontext_t structure are 8 bytes long for both MIPS32/MIPS64. get/set/make/swap context implementations for MIPS O32 incorrectly assume that general purpose registers in this structure are 4 bytes long. This patch is fixing that. Tested for MIPS O32 LE and BE. Compared objdump of modified functions for mips n32 and mips n64. [BZ #21548] * sysdeps/unix/sysv/linux/mips/getcontext.S: Define MCONTEXT_SZGREG as 8 and use it when copying general purpose registers. * sysdeps/unix/sysv/linux/mips/makecontext.S: Likewise. * sysdeps/unix/sysv/linux/mips/mips32/Makefile: Include new test for mips o32. * sysdeps/unix/sysv/linux/mips/mips32/bug-getcontext-mips-gp.c: Added new test for mips o32. * sysdeps/unix/sysv/linux/mips/setcontext.S: Define MCONTEXT_SZGREG as 8 and use it when copying general purpose registers. * sysdeps/unix/sysv/linux/mips/swapcontext.S: Likewise.
Diffstat (limited to 'sysdeps/unix/sysv/linux/mips/setcontext.S')
| -rw-r--r-- | sysdeps/unix/sysv/linux/mips/setcontext.S | 51 |
1 files changed, 29 insertions, 22 deletions
diff --git a/sysdeps/unix/sysv/linux/mips/setcontext.S b/sysdeps/unix/sysv/linux/mips/setcontext.S index 4e363d98d0..4f52b8d460 100644 --- a/sysdeps/unix/sysv/linux/mips/setcontext.S +++ b/sysdeps/unix/sysv/linux/mips/setcontext.S @@ -47,6 +47,12 @@ A0OFF = FRAMESZ - (1 * SZREG) /* callee-allocated */ #else A0OFF = FRAMESZ + (0 * SZREG) /* caller-allocated */ #endif +MCONTEXT_GREGSZ = 8 +#if _MIPS_SIM == _ABIO32 && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +MCONTEXT_GREGOFF = 4 +#else +MCONTEXT_GREGOFF = 0 +#endif NESTED (__setcontext, FRAMESZ, ra) .mask MASK, -(ARGSZ * SZREG) @@ -73,7 +79,8 @@ NESTED (__setcontext, FRAMESZ, ra) /* Check for the magic flag. */ li v0, 1 - REG_L v1, (0 * SZREG + MCONTEXT_GREGS)(a0) /* zero */ + /* zero */ + REG_L v1, (MCONTEXT_GREGOFF + 0 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(a0) bne v0, v1, 98f REG_S a0, A0OFF(sp) @@ -117,32 +124,32 @@ NESTED (__setcontext, FRAMESZ, ra) /* Note the contents of argument registers will be random unless makecontext() has been called. */ - REG_L a0, (4 * SZREG + MCONTEXT_GREGS)(v0) - REG_L a1, (5 * SZREG + MCONTEXT_GREGS)(v0) - REG_L a2, (6 * SZREG + MCONTEXT_GREGS)(v0) - REG_L a3, (7 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a0, (MCONTEXT_GREGOFF + 4 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L a1, (MCONTEXT_GREGOFF + 5 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L a2, (MCONTEXT_GREGOFF + 6 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L a3, (MCONTEXT_GREGOFF + 7 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) #if _MIPS_SIM != _ABIO32 - REG_L a4, (8 * SZREG + MCONTEXT_GREGS)(v0) - REG_L a5, (9 * SZREG + MCONTEXT_GREGS)(v0) - REG_L a6, (10 * SZREG + MCONTEXT_GREGS)(v0) - REG_L a7, (11 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a4, (MCONTEXT_GREGOFF + 8 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L a5, (MCONTEXT_GREGOFF + 9 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L a6, (MCONTEXT_GREGOFF + 10 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L a7, (MCONTEXT_GREGOFF + 11 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) #endif - REG_L s0, (16 * SZREG + MCONTEXT_GREGS)(v0) - REG_L s1, (17 * SZREG + MCONTEXT_GREGS)(v0) - REG_L s2, (18 * SZREG + MCONTEXT_GREGS)(v0) - REG_L s3, (19 * SZREG + MCONTEXT_GREGS)(v0) - REG_L s4, (20 * SZREG + MCONTEXT_GREGS)(v0) - REG_L s5, (21 * SZREG + MCONTEXT_GREGS)(v0) - REG_L s6, (22 * SZREG + MCONTEXT_GREGS)(v0) - REG_L s7, (23 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s0, (MCONTEXT_GREGOFF + 16 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L s1, (MCONTEXT_GREGOFF + 17 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L s2, (MCONTEXT_GREGOFF + 18 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L s3, (MCONTEXT_GREGOFF + 19 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L s4, (MCONTEXT_GREGOFF + 20 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L s5, (MCONTEXT_GREGOFF + 21 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L s6, (MCONTEXT_GREGOFF + 22 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L s7, (MCONTEXT_GREGOFF + 23 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) #if ! defined (__PIC__) || _MIPS_SIM != _ABIO32 - REG_L gp, (28 * SZREG + MCONTEXT_GREGS)(v0) + REG_L gp, (MCONTEXT_GREGOFF + 28 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) #endif - REG_L sp, (29 * SZREG + MCONTEXT_GREGS)(v0) - REG_L fp, (30 * SZREG + MCONTEXT_GREGS)(v0) - REG_L ra, (31 * SZREG + MCONTEXT_GREGS)(v0) - REG_L t9, MCONTEXT_PC(v0) + REG_L sp, (MCONTEXT_GREGOFF + 29 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L fp, (MCONTEXT_GREGOFF + 30 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L ra, (MCONTEXT_GREGOFF + 31 * MCONTEXT_GREGSZ + MCONTEXT_GREGS)(v0) + REG_L t9, (MCONTEXT_GREGOFF + MCONTEXT_PC)(v0) move v0, zero jr t9 |