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| author | Zong Li <zongbox@gmail.com> | 2018-11-30 17:18:00 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-08-27 08:17:43 -0700 |
| commit | 72dfddeffcc993a726bdcbe5e515afa1180095e8 (patch) | |
| tree | c164b32b945df48e74ad88e1f4e539bd44a4b5de /sysdeps/riscv/preconfigure | |
| parent | 30b963c143eaa07f09567f2e0649edb7525c43fd (diff) | |
| download | glibc-72dfddeffcc993a726bdcbe5e515afa1180095e8.tar.gz glibc-72dfddeffcc993a726bdcbe5e515afa1180095e8.tar.xz glibc-72dfddeffcc993a726bdcbe5e515afa1180095e8.zip | |
RISC-V: Build infrastructure for 32-bit port
This patch lays out the top-level organisation of the RISC-V 32-bit port. It provides all the Implies files as well as various other fragments of the build infrastructure. Reviewed-by: Maciej W. Rozycki <macro@wdc.com>
Diffstat (limited to 'sysdeps/riscv/preconfigure')
| -rw-r--r-- | sysdeps/riscv/preconfigure | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/sysdeps/riscv/preconfigure b/sysdeps/riscv/preconfigure index d9adb31b64..1ab5d20f0e 100644 --- a/sysdeps/riscv/preconfigure +++ b/sysdeps/riscv/preconfigure @@ -6,11 +6,7 @@ riscv*) atomic=`$CC $CFLAGS $CPPFLAGS -E -dM -xc /dev/null | grep '#define __riscv_atomic' | cut -d' ' -f2` case "$xlen" in - 32) - echo "glibc does not yet support 32-bit systems" >&2 - exit 1 - ;; - 64) + 64 | 32) ;; *) echo "Unable to determine XLEN" >&2 |