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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2023-10-05 17:10:52 +0100 |
|---|---|---|
| committer | Szabolcs Nagy <szabolcs.nagy@arm.com> | 2023-10-23 15:00:45 +0100 |
| commit | 31aaf6fed986fade042f9ffe7535d8b3f2c173a2 (patch) | |
| tree | 5417d6dffd8eefa74a1506a792ed40330205ce31 /sysdeps/pthread/tst-spin4.c | |
| parent | 067a34156c19fb3c53824e37d70820c0ce5b87b2 (diff) | |
| download | glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.tar.gz glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.tar.xz glibc-31aaf6fed986fade042f9ffe7535d8b3f2c173a2.zip | |
aarch64: Add vector implementations of exp10 routines
Double-precision routines either reuse the exp table (AdvSIMD) or use SVE FEXPA intruction.
Diffstat (limited to 'sysdeps/pthread/tst-spin4.c')
0 files changed, 0 insertions, 0 deletions