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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 09:43:51 -0600 |
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| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 12:58:32 -0600 |
| commit | 487972aea52004f604c2878c8c9d3e77670f2c32 (patch) | |
| tree | 1f8a570e52975d04c513523e7d7b454a29015993 /sysdeps/powerpc/powerpc64/power8/fpu/s_isinff.S | |
| parent | 7d92b78723848ae616709eb8f0191ea067025b18 (diff) | |
| download | glibc-487972aea52004f604c2878c8c9d3e77670f2c32.tar.gz glibc-487972aea52004f604c2878c8c9d3e77670f2c32.tar.xz glibc-487972aea52004f604c2878c8c9d3e77670f2c32.zip | |
PowerPC: Optimized isnan/isnanf for POWER8
This patch add a optimized isnan/isnanf implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/power8/fpu/s_isinff.S')
0 files changed, 0 insertions, 0 deletions