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| author | Ulrich Drepper <drepper@redhat.com> | 2007-07-12 18:38:01 +0000 |
|---|---|---|
| committer | Ulrich Drepper <drepper@redhat.com> | 2007-07-12 18:38:01 +0000 |
| commit | a88f47a72f4ca65832584a3f5a591690f6675092 (patch) | |
| tree | 6876a751bd4c5c3fab26e1a323a4f63a166e01cc /sysdeps/powerpc/powerpc64/power4/memset.S | |
| parent | 1c298d08873e72a2339161517da660bdaff0e3f8 (diff) | |
| download | glibc-a88f47a72f4ca65832584a3f5a591690f6675092.tar.gz glibc-a88f47a72f4ca65832584a3f5a591690f6675092.tar.xz glibc-a88f47a72f4ca65832584a3f5a591690f6675092.zip | |
* sysdeps/powerpc/powerpc32/power6/memset.S: Update comments.
Specify .machine power6 to get ISA-V2.0 branch hints. Unroll loops and avoid branch misspredicts for > 31 bytes memset case. * sysdeps/powerpc/powerpc64/power6/memset.S: Likewise. Remove toc ref to __cache_line_size. * sysdeps/powerpc/powerpc32/power4/memcmp.S: Specify .machine power4 to get ISA-V2.0 branch hints. * sysdeps/powerpc/powerpc32/power4/memcpy.S: Likewise * sysdeps/powerpc/powerpc32/power4/memset.S: Likewise * sysdeps/powerpc/powerpc32/power6/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcmp.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memcpy.S: Likewise. * sysdeps/powerpc/powerpc64/power4/memset.S: Likewise. Remove toc ref to __cache_line_size. * sysdeps/powerpc/powerpc32/power6/fpu/s_llrint.S: Include math_ldbl_opt.h.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/power4/memset.S')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/power4/memset.S | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/sysdeps/powerpc/powerpc64/power4/memset.S b/sysdeps/powerpc/powerpc64/power4/memset.S index 17b2d76950..e7a259acdd 100644 --- a/sysdeps/powerpc/powerpc64/power4/memset.S +++ b/sysdeps/powerpc/powerpc64/power4/memset.S @@ -22,12 +22,6 @@ #include <bp-sym.h> #include <bp-asm.h> - .section ".toc","aw" -.LC0: - .tc __cache_line_size[TC],__cache_line_size - .section ".text" - .align 2 - /* __ptr_t [r3] memset (__ptr_t s [r3], int c [r4], size_t n [r5])); Returns 's'. @@ -35,6 +29,7 @@ cache line (256 bits). There is a special case for setting cache lines to 0, to take advantage of the dcbz instruction. */ + .machine power4 EALIGN (BP_SYM (memset), 5, 0) CALL_MCOUNT 3 |