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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-18 09:29:29 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-02-27 12:58:33 -0600 |
| commit | 1ad8950a3ea4056ed343d681b5146f4b4aa27e10 (patch) | |
| tree | 4dff22d7793de4244498f8c384dea196eb47a5a1 /sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c | |
| parent | cac626d60a863e48ab75417064984769e58c5719 (diff) | |
| download | glibc-1ad8950a3ea4056ed343d681b5146f4b4aa27e10.tar.gz glibc-1ad8950a3ea4056ed343d681b5146f4b4aa27e10.tar.xz glibc-1ad8950a3ea4056ed343d681b5146f4b4aa27e10.zip | |
PowerPC: llrint/llrintf POWER8 optimization
This patch add a optimized llrint/llrintf implementation for POWER8 using the new Move From VSR Doubleword instruction to gains some cycles from FP to GRP register move.
Diffstat (limited to 'sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c')
| -rw-r--r-- | sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c b/sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c index 5818b53c09..cf1b2e4e5a 100644 --- a/sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c +++ b/sysdeps/powerpc/powerpc64/fpu/multiarch/s_llrint.c @@ -30,10 +30,13 @@ extern __typeof (__llrint) __llrint_ppc64 attribute_hidden; extern __typeof (__llrint) __llrint_power6x attribute_hidden; +extern __typeof (__llrint) __llrint_power8 attribute_hidden; libc_ifunc (__llrint, - (hwcap & PPC_FEATURE_POWER6_EXT) - ? __llrint_power6x + (hwcap2 & PPC_FEATURE2_ARCH_2_07) + ? __llrint_power8 : + (hwcap & PPC_FEATURE_POWER6_EXT) + ? __llrint_power6x : __llrint_ppc64); weak_alias (__llrint, llrint) |