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| author | Joseph Myers <joseph@codesourcery.com> | 2016-10-19 22:58:34 +0000 |
|---|---|---|
| committer | Joseph Myers <joseph@codesourcery.com> | 2016-10-19 22:58:34 +0000 |
| commit | 05f3ed0a799d08c2b3ecc256fc0dc08d8b9a3784 (patch) | |
| tree | 1904f26eb95916cec76cb876dbe163bb72593235 /sysdeps/powerpc/powerpc32 | |
| parent | f8e8b8ed9f266097b42a77359445372d82365916 (diff) | |
| download | glibc-05f3ed0a799d08c2b3ecc256fc0dc08d8b9a3784.tar.gz glibc-05f3ed0a799d08c2b3ecc256fc0dc08d8b9a3784.tar.xz glibc-05f3ed0a799d08c2b3ecc256fc0dc08d8b9a3784.zip | |
Stop powerpc copysignl raising "invalid" for sNaN argument (bug 20718).
The powerpc (hard-float) implementations of copysignl, both 32-bit and 64-bit, raise spurious "invalid" exceptions when the first argument is a signaling NaN. copysign functions should never raise exceptions even for signaling NaNs. The problem is the use of an fcmpu instruction to test the sign of the high part of the long double argument. This patch fixes the functions to use fsel instead (as used for fabsl following my fixes for a similar bug there), or to examine the integer representation for older 32-bit processors without fsel. Tested for powerpc64 and powerpc32 (configurations with and without fsel used). [BZ #20718] * sysdeps/powerpc/powerpc32/fpu/s_copysignl.S (__copysignl): Do not use floating-point comparisons to test sign. * sysdeps/powerpc/powerpc64/fpu/s_copysignl.S (__copysignl): Likewise.
Diffstat (limited to 'sysdeps/powerpc/powerpc32')
| -rw-r--r-- | sysdeps/powerpc/powerpc32/fpu/s_copysignl.S | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S b/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S index aed783ad59..1eec8474ed 100644 --- a/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S +++ b/sysdeps/powerpc/powerpc32/fpu/s_copysignl.S @@ -24,22 +24,39 @@ ENTRY(__copysignl) /* long double [f1,f2] copysign (long double [f1,f2] x, long double [f3,f4] y); copysign(x,y) returns a value with the magnitude of x and with the sign bit of y. */ +#ifdef _ARCH_PPCGR + /* fsel available. */ stwu r1,-16(r1) cfi_adjust_cfa_offset (16) stfd fp3,8(r1) fmr fp0,fp1 fabs fp1,fp1 - fcmpu cr7,fp0,fp1 lwz r3,8+HIWORD(r1) cmpwi cr6,r3,0 addi r1,r1,16 cfi_adjust_cfa_offset (-16) - beq cr7,L(0) + fneg fp3,fp2 + fsel fp2,fp0,fp2,fp3 + bgelr cr6 + fneg fp1,fp1 fneg fp2,fp2 -L(0): bgelr cr6 + blr +#else + stwu r1,-32(r1) + cfi_adjust_cfa_offset (32) + stfd fp3,8(r1) + stfd fp1,16(r1) + lwz r3,8+HIWORD(r1) + lwz r4,16+HIWORD(r1) + xor r3,r3,r4 + cmpwi cr6,r3,0 + addi r1,r1,32 + cfi_adjust_cfa_offset (-32) + bgelr cr6 fneg fp1,fp1 fneg fp2,fp2 blr +#endif END (__copysignl) #if IS_IN (libm) |