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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-06-25 11:54:31 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-07-07 15:41:27 -0500 |
| commit | 87868c2418fb74357757e3b739ce5b76b17a8929 (patch) | |
| tree | 9ec2b1d9a4c0cf6af2a4306e09a11fc992bea94c /sysdeps/powerpc/powerpc32/power7 | |
| parent | 07aedd78b095093e866efd4809a80090e2b91a0b (diff) | |
| download | glibc-87868c2418fb74357757e3b739ce5b76b17a8929.tar.gz glibc-87868c2418fb74357757e3b739ce5b76b17a8929.tar.xz glibc-87868c2418fb74357757e3b739ce5b76b17a8929.zip | |
PowerPC: Align power7 memcpy using VSX to quadword
This patch changes power7 memcpy to use VSX instructions only when memory is aligned to quardword. It is to avoid unaligned kernel traps on non-cacheable memory (for instance, memory-mapped I/O).
Diffstat (limited to 'sysdeps/powerpc/powerpc32/power7')
| -rw-r--r-- | sysdeps/powerpc/powerpc32/power7/memcpy.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sysdeps/powerpc/powerpc32/power7/memcpy.S b/sysdeps/powerpc/powerpc32/power7/memcpy.S index 52c2a6bcf4..e540fead87 100644 --- a/sysdeps/powerpc/powerpc32/power7/memcpy.S +++ b/sysdeps/powerpc/powerpc32/power7/memcpy.S @@ -38,8 +38,8 @@ EALIGN (memcpy, 5, 0) ble cr1, L(copy_LT_32) /* If move < 32 bytes use short move code. */ - andi. 11,3,7 /* Check alignment of DST. */ - clrlwi 10,4,29 /* Check alignment of SRC. */ + andi. 11,3,15 /* Check alignment of DST. */ + clrlwi 10,4,28 /* Check alignment of SRC. */ cmplw cr6,10,11 /* SRC and DST alignments match? */ mr 12,4 mr 31,5 |