Fix spelling errors in sysdeps/powerpc files.

3 files changed, 4 insertions, 4 deletions

diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c
index c91645560a..671724b287 100644
--- a/sysdeps/powerpc/fpu/feholdexcpt.c
+++ b/sysdeps/powerpc/fpu/feholdexcpt.c
@@ -33,7 +33,7 @@ feholdexcept (fenv_t *envp)
   new.l[1] = old.l[1] & 7;
   new.l[0] = old.l[0];
   
-  /* If the old env had any eabled exceptions, then mask SIGFPE in the
+  /* If the old env had any enabled exceptions, then mask SIGFPE in the
      MSR FE0/FE1 bits.  This may allow the FPU to run faster because it
      always takes the default action and can not generate SIGFPE. */
   if ((old.l[1] & _FPU_MASK_ALL) != 0)
diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c
index 30f8a6b6c6..66f2826398 100644
--- a/sysdeps/powerpc/fpu/feupdateenv.c
+++ b/sysdeps/powerpc/fpu/feupdateenv.c
@@ -37,14 +37,14 @@ __feupdateenv (const fenv_t *envp)
      unchanged.  */
   new.l[1] = (old.l[1] & 0x1FFFFF00) | (new.l[1] & 0x1FF80FFF);
   
-  /* If the old env has no eabled exceptions and the new env has any enabled
+  /* If the old env has no enabled exceptions and the new env has any enabled
      exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits.  This will put
      the hardware into "precise mode" and may cause the FPU to run slower on
      some hardware.  */
   if ((old.l[1] & _FPU_MASK_ALL) == 0 && (new.l[1] & _FPU_MASK_ALL) != 0)
     (void)__fe_nomask_env ();
   
-  /* If the old env had any eabled exceptions and the new env has no enabled
+  /* If the old env had any enabled exceptions and the new env has no enabled
      exceptions, then mask SIGFPE in the MSR FE0/FE1 bits.  This may allow the
      FPU to run faster because it always takes the default action and can not 
      generate SIGFPE. */
diff --git a/sysdeps/powerpc/fpu/math_ldbl.h b/sysdeps/powerpc/fpu/math_ldbl.h
index 6cd6d0bdfe..20224e6646 100644
--- a/sysdeps/powerpc/fpu/math_ldbl.h
+++ b/sysdeps/powerpc/fpu/math_ldbl.h
@@ -27,7 +27,7 @@ ldbl_extract_mantissa (int64_t *hi64, u_int64_t *lo64, int *exp, long double x)
       lo |= (1ULL << 52);
       lo = lo << 7; /* pre-shift lo to match ieee854.  */
       /* The lower double is normalized separately from the upper.  We
-	 may need to adjust the lower manitissa to reflect this.  */
+	 may need to adjust the lower mantissa to reflect this.  */
       ediff = eldbl.ieee.exponent - eldbl.ieee.exponent2;
       if (ediff > 53)
 	lo = lo >> (ediff-53);