Update.

	* Versions.def (libm): Add GLIBC_2.1.3.

	ISO C99 TR1 changes various fe* functions to return an error value.
	* math/Versions [GLIBC_2.1.3]: Add feclearexcept, fegetexceptflag,
	feraiseexcept, fesetexceptflag, fegetenv, fesetenv, and feupdateenv.
	* sysdeps/alpha/fpu/fclrexcpt.c: Return value and add alias.
	* sysdeps/alpha/fpu/fegetenv.c: Likewise.
	* sysdeps/alpha/fpu/fesetenv.c: Likewise.
	* sysdeps/alpha/fpu/feupdateenv.c: Likewise.
	* sysdeps/alpha/fpu/fgetexcptflg.c: Likewise.
	* sysdeps/alpha/fpu/fraiseexcpt.c: Likewise.
	* sysdeps/alpha/fpu/fsetexcptflg.c: Likewise.
	* sysdeps/arm/fpu/fclrexcpt.c: Likewise.
	* sysdeps/arm/fpu/fegetenv.c: Likewise.
	* sysdeps/arm/fpu/fesetenv.c: Likewise.
	* sysdeps/arm/fpu/fraiseexcpt.c: Likewise.
	* sysdeps/arm/fpu/fsetexcptflg.c: Likewise.
	* sysdeps/generic/fclrexcpt.c: Likewise.
	* sysdeps/generic/fegetenv.c: Likewise.
	* sysdeps/generic/fesetenv.c: Likewise.
	* sysdeps/generic/feupdateenv.c: Likewise.
	* sysdeps/generic/fgetexcptflg.c: Likewise.
	* sysdeps/generic/fraiseexcpt.c: Likewise.
	* sysdeps/generic/fsetexcptflg.c: Likewise.
	* sysdeps/i386/fpu/fclrexcpt.c: Likewise.
	* sysdeps/i386/fpu/fegetenv.c: Likewise.
	* sysdeps/i386/fpu/fesetenv.c: Likewise.
	* sysdeps/i386/fpu/feupdateenv.c: Likewise.
	* sysdeps/i386/fpu/fgetexcptflg.c: Likewise.
	* sysdeps/i386/fpu/fraiseexcpt.c: Likewise.
	* sysdeps/i386/fpu/fsetexcptflg.c: Likewise.
	* sysdeps/m68k/fpu/fclrexcpt.c: Likewise.
	* sysdeps/m68k/fpu/fegetenv.c: Likewise.
	* sysdeps/m68k/fpu/fesetenv.c: Likewise.
	* sysdeps/m68k/fpu/feupdateenv.c: Likewise.
	* sysdeps/m68k/fpu/fgetexcptflg.c: Likewise.
	* sysdeps/m68k/fpu/fraiseexcpt.c: Likewise.
	* sysdeps/m68k/fpu/fsetexcptflg.c: Likewise.
	* sysdeps/mips/fclrexcpt.c: Likewise.
	* sysdeps/mips/fegetenv.c: Likewise.
	* sysdeps/mips/fesetenv.c: Likewise.
	* sysdeps/mips/feupdateenv.c: Likewise.
	* sysdeps/mips/fgetexcptflg.c: Likewise.
	* sysdeps/powerpc/fclrexcpt.c: Likewise.
	* sysdeps/powerpc/fegetenv.c: Likewise.
	* sysdeps/powerpc/fesetenv.c: Likewise.
	* sysdeps/powerpc/feupdateenv.c: Likewise.
	* sysdeps/powerpc/fgetexcptflg.c: Likewise.
	* sysdeps/powerpc/fraiseexcpt.c: Likewise.
	* sysdeps/powerpc/fsetexcptflg.c: Likewise.
	* sysdeps/sparc/fpu/fclrexcpt.c: Likewise.
	* sysdeps/sparc/fpu/fegetenv.c: Likewise.
	* sysdeps/sparc/fpu/fesetenv.c: Likewise.
	* sysdeps/sparc/fpu/feupdateenv.c: Likewise.
	* sysdeps/sparc/fpu/fgetexcptflg.c: Likewise.
	* sysdeps/sparc/fpu/fraiseexcpt.c: Likewise.
	* sysdeps/sparc/fpu/fsetexcptflg.c: Likewise.
	* math/fenv.h: Adjust prototypes.: Likewise.
	* manual/arith.texi: Adjust documentation for these changes.

	* manual/arith.texi: Document feraiseexcept.

	* sysdeps/powerpc/fegetenv.c: Moved to...
	* sysdeps/powerpc/fpu/fegetenv.c: ...here.
	* sysdeps/powerpc/fegetround.c: Moved to...
	* sysdeps/powerpc/fpu/fegetround.c: ...here.
	* sysdeps/powerpc/feholdexcpt.c: Moved to...
	* sysdeps/powerpc/fpu/feholdexcpt.c: ...here.
	* sysdeps/powerpc/fesetenv.c: Moved to...
	* sysdeps/powerpc/fpu/fesetenv.c: ...here.
	* sysdeps/powerpc/fenv_libc.h: Moved to...
	* sysdeps/powerpc/fpu/fenv_libc.h: ...here.
	* sysdeps/powerpc/feupdateenv.c: Moved to...
	* sysdeps/powerpc/fpu/feupdateenv.c: ...here.
	* sysdeps/powerpc/fgetexcptflg.c: Moved to...
	* sysdeps/powerpc/fpu/fgetexcptflg.c: ...here.
	* sysdeps/powerpc/fraiseexcpt.c: Moved to...
	* sysdeps/powerpc/fpu/fraiseexcpt.c: ...here.
	* sysdeps/powerpc/fsetexcptflg.c: Moved to...
	* sysdeps/powerpc/fpu/fsetexcptflg.c: ...here.
	* sysdeps/powerpc/ftestexcept.c: Moved to...
	* sysdeps/powerpc/fpu/ftestexcept.c: ...here.
	* sysdeps/powerpc/fesetround.c: Moved to...
	* sysdeps/powerpc/fpu/fesetround.c: ...here
	* sysdeps/powerpc/fenv_const.c: Moved to...
	* sysdeps/powerpc/fpu/fenv_const.c: ...here.

1999-10-29  Jakub Jelinek  <jakub@redhat.com>

	* stdlib/longlong.h: Avoid UDIV_TIME redefinition.
	* sysdeps/sparc/sparc32/dl-machine.h: Fix loading of SPARC v8plus
	libraries from statically linked programs.
	* sysdeps/unix/sysv/linux/sparc/bits/sigaction.h: POSIX 199309
	fix for sigaction on SPARC.
	Patches by David S. Miller <davem@redhat.com>.

	* sysdeps/unix/sysv/linux/sparc/sys/ucontext.h: Declare
	gregset_t and other required structures and defines for SPARC 64bit
	ABI as well, not only 32bit ABI.

1999-10-31  Andreas Jaeger  <aj@suse.de>

	* sysdeps/sparc/sparc64/fpu/bits/huge_val.h: Replace __USE_ISOC9X
	by __USE_ISOC99 and update comments.

	* math/complex.h: Update comments for ISO C99.
	* math/fenv.h: Likewise.
	* math/test-fenv.c: Likewise.
	* math/tgmath.h: Likewise.
	* libio/stdio.h: Likewise.
	* posix/sys/types.h: Likewise.
	* sysdeps/generic/inttypes.h: Likewise.
	* sysdeps/generic/stdint.h: Likewise.

1999-10-31  Ulrich Drepper  <drepper@cygnus.com>

1 files changed, 106 insertions, 0 deletions

diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h
new file mode 100644
index 0000000000..343be16fcb
--- /dev/null
+++ b/sysdeps/powerpc/fpu/fenv_libc.h
@@ -0,0 +1,106 @@
+/* Internal libc stuff for floating point environment routines.
+   Copyright (C) 1997 Free Software Foundation, Inc.
+   This file is part of the GNU C Library.
+
+   The GNU C Library is free software; you can redistribute it and/or
+   modify it under the terms of the GNU Library General Public License as
+   published by the Free Software Foundation; either version 2 of the
+   License, or (at your option) any later version.
+
+   The GNU C Library is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   Library General Public License for more details.
+
+   You should have received a copy of the GNU Library General Public
+   License along with the GNU C Library; see the file COPYING.LIB.  If not,
+   write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#ifndef _FENV_LIBC_H
+#define _FENV_LIBC_H	1
+
+#include <fenv.h>
+
+/* The sticky bits in the FPSCR indicating exceptions have occurred.  */
+#define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID)
+
+/* Equivalent to fegetenv, but returns a fenv_t instead of taking a
+   pointer.  */
+#define fegetenv_register() \
+        ({ fenv_t env; asm volatile ("mffs %0" : "=f" (env)); env; })
+
+/* Equivalent to fesetenv, but takes a fenv_t instead of a pointer.  */
+#define fesetenv_register(env) \
+        ({ double d = (env); asm volatile ("mtfsf 0xff,%0" : : "f" (d)); })
+
+/* This very handy macro:
+   - Sets the rounding mode to 'round to nearest';
+   - Sets the processor into IEEE mode; and
+   - Prevents exceptions from being raised for inexact results.
+   These things happen to be exactly what you need for typical elementary
+   functions.  */
+#define relax_fenv_state() asm ("mtfsfi 7,0")
+
+/* Set/clear a particular FPSCR bit (for instance,
+   reset_fpscr_bit(FPSCR_VE);
+   prevents INVALID exceptions from being raised).  */
+#define set_fpscr_bit(x) asm volatile ("mtfsb1 %0" : : "i"(x))
+#define reset_fpscr_bit(x) asm volatile ("mtfsb0 %0" : : "i"(x))
+
+typedef union
+{
+  fenv_t fenv;
+  unsigned int l[2];
+} fenv_union_t;
+
+/* Definitions of all the FPSCR bit numbers */
+enum {
+  FPSCR_FX = 0,    /* exception summary */
+  FPSCR_FEX,       /* enabled exception summary */
+  FPSCR_VX,        /* invalid operation summary */
+  FPSCR_OX,        /* overflow */
+  FPSCR_UX,        /* underflow */
+  FPSCR_ZX,        /* zero divide */
+  FPSCR_XX,        /* inexact */
+  FPSCR_VXSNAN,    /* invalid operation for SNaN */
+  FPSCR_VXISI,     /* invalid operation for Inf-Inf */
+  FPSCR_VXIDI,     /* invalid operation for Inf/Inf */
+  FPSCR_VXZDZ,     /* invalid operation for 0/0 */
+  FPSCR_VXIMZ,     /* invalid operation for Inf*0 */
+  FPSCR_VXVC,      /* invalid operation for invalid compare */
+  FPSCR_FR,        /* fraction rounded [fraction was incremented by round] */
+  FPSCR_FI,        /* fraction inexact */
+  FPSCR_FPRF_C,    /* result class descriptor */
+  FPSCR_FPRF_FL,   /* result less than (usually, less than 0) */
+  FPSCR_FPRF_FG,   /* result greater than */
+  FPSCR_FPRF_FE,   /* result equal to */
+  FPSCR_FPRF_FU,   /* result unordered */
+  FPSCR_20,        /* reserved */
+  FPSCR_VXSOFT,    /* invalid operation set by software */
+  FPSCR_VXSQRT,    /* invalid operation for square root */
+  FPSCR_VXCVI,     /* invalid operation for invalid integer convert */
+  FPSCR_VE,        /* invalid operation exception enable */
+  FPSCR_OE,        /* overflow exception enable */
+  FPSCR_UE,        /* underflow exception enable */
+  FPSCR_ZE,        /* zero divide exception enable */
+  FPSCR_XE,        /* inexact exception enable */
+  FPSCR_NI         /* non-IEEE mode (typically, no denormalised numbers) */
+  /* the remaining two least-significant bits keep the rounding mode */
+};
+
+/* This operation (i) sets the appropriate FPSCR bits for its
+   parameter, (ii) converts SNaN to the corresponding NaN, and (iii)
+   otherwise passes its parameter through unchanged (in particular, -0
+   and +0 stay as they were).  The `obvious' way to do this is optimised
+   out by gcc.  */
+#define f_wash(x) \
+   ({ double d; asm volatile ("fmul %0,%1,%2" \
+			      : "=f"(d) \
+			      : "f" (x), "f"((float)1.0)); d; })
+#define f_washf(x) \
+   ({ float f; asm volatile ("fmuls %0,%1,%2" \
+			     : "=f"(f) \
+			     : "f" (x), "f"((float)1.0)); f; })
+ 
+#endif /* fenv_libc.h */