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| author | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-28 14:38:24 -0500 |
|---|---|---|
| committer | Adhemerval Zanella <azanella@linux.vnet.ibm.com> | 2014-04-29 07:05:39 -0500 |
| commit | 18f2945ae9216cfcd53a162080a73e3d719de9e6 (patch) | |
| tree | 8d529fe01c41f0d3c6dd290aa69dbf4e5d6e083f /sysdeps/powerpc/fpu/fclrexcpt.c | |
| parent | 5abebba403181de898bbea4ee1bcce5f088c663b (diff) | |
| download | glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.gz glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.tar.xz glibc-18f2945ae9216cfcd53a162080a73e3d719de9e6.zip | |
PowerPC: Suppress unnecessary FPSCR write
This patch optimizes the FPSCR update on exception and rounding change functions by just updating its value if new value if different from current one. It also optimizes fedisableexcept and feenableexcept by removing an unecessary FPSCR read.
Diffstat (limited to 'sysdeps/powerpc/fpu/fclrexcpt.c')
| -rw-r--r-- | sysdeps/powerpc/fpu/fclrexcpt.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/sysdeps/powerpc/fpu/fclrexcpt.c b/sysdeps/powerpc/fpu/fclrexcpt.c index cda2810120..4607f62bb1 100644 --- a/sysdeps/powerpc/fpu/fclrexcpt.c +++ b/sysdeps/powerpc/fpu/fclrexcpt.c @@ -22,17 +22,18 @@ int __feclearexcept (int excepts) { - fenv_union_t u; + fenv_union_t u, n; /* Get the current state. */ u.fenv = fegetenv_register (); /* Clear the relevant bits. */ - u.l = u.l & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID) + n.l = u.l & ~((-(excepts >> (31 - FPSCR_VX) & 1) & FE_ALL_INVALID) | (excepts & FPSCR_STICKY_BITS)); /* Put the new state in effect. */ - fesetenv_register (u.fenv); + if (u.l != n.l) + fesetenv_register (n.fenv); /* Success. */ return 0; |